Abstract: A method for depositing tungsten nitride uses a source gas mixture having a silicon based gas, such as silane for depositing the tungsten nitride to overlie a deposition substrate. A non-planar storage capacitor has a tungsten nitride capacitor electrode.

Abstract: A Ti.sub.x N.sub.y layer, not necessarily stoichiometric, is interposed between a titanium or aluminum interconnect layer to improve adhesion and prevent re-entrant undercutting and lifting of the interconnect layer during the process of patterning and plasma etching to form interconnect lines on a substrate, such as an oxide.

Abstract: The invention disclosed herein is a semiconductor die assembly and method of making the same having a die and insert substrate that are electrically interconnected by diffusing gold bumps attached to the connecting surface of the substrate to aluminum-based bond pads on the die to form a permanent die-to-insert connection. The process for diffusing the gold bumps into the bond pads preferably occurs during a burn-in process wherein pressure and heat are applied to the die/substrate assembly without melting the gold bumps until a permanent die-to-insert substrate connection is properly made.

Abstract: The specification describes a process for siliciding silicon metallization with titanium. The process requires two anneal steps and is based on careful control of operating parameters during the first anneal step. A prescription is given relating time and temperature of anneal, and titanium film thickness, to silicide resistivity. Proper choice of parameters also minimizes variables in the process.

Abstract: Method for filling contact holes with metals by two-step deposition of selective tungsten layer is disclosed. The selective tungsten thin films are deposited in two steps, thus maximizing the contact filling with tungsten, gaining a stability of metal wires with better step coverage, and enhancing the reliability on semiconductor element.

Abstract: A method or utilizing electroless copper deposition to selectively form encapsulated copper plugs to connect conductive regions on a semiconductor. A via opening in an inter-level dielectric (ILD) provides a path for connecting two conductive regions separated by the ILD. Once the underlying metal layer is exposed by the via opening, a SiN or SiON dielectric encapsulation layer is formed along the sidewalls of the via. Then, a contact displacement technique is used to form a thin activation layer of copper on a barrier metal, such as TiN, which is present as a covering layer on the underlying metal layer. After the contact displacement of copper on the barrier layer at the bottom of the via, an electroless copper deposition technique is then used to auto-catalytically deposit copper in the via. The electroless copper deposition continues until the via is almost filled, but leaving sufficient room at the top in order to form an upper encapsulation layer.

Abstract: A method for efficiently removing by-products produced in dry-etching a fabricated structure of a semiconductor device, particularly, a polycide structure. The method includes the steps of sequentially forming a polysilicon layer and a refractory metal silicide layer to overlie previously fabricated structures on a semiconductor substrate, dry-etching the polysilicon layer and the refractory metal silicide layer to form a patterned polysilicon layer and a patterned refractory metal silicide layer, and thermal treating the resultant structure to remove at least one kind of by-product produced in the dry-etching step at a temperature higher than the boiling point of any by-product.

Abstract: A method for reducing resistance in the fabrication of a silicided polysilicon gate for a very small transistor integrated circuit device is described. A polysilicon layer is deposited overlying a gate silicon oxide layer. The polysilicon and gate oxide layers are etched away where they are not covered by a mask to form a gate electrode. Ions are implanted to form source and drain regions within the semiconductor substrate using the gate electrode as a mask. A dielectric layer is deposited overlying the semiconductor substrate and the gate electrode. The dielectric layer is anisotropically etched to leave first spacers on the sidewalls of the gate electrode. The first spacers are isotropically etched back to leave second spacers extending approximately halfway up on the sidewalls of the gate electrode. A layer of titanium is conformally deposited over the surfaces of the substrate. The substrate is annealed whereby the titanium layer is transformed into a titanium silicide layer.

Abstract: A new method of metallization using a tungsten plug is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer covers the semiconductor device structures wherein a contact opening is made through the insulating layer to the semiconductor substrate. A barrier layer is deposited conformally over the surface of the insulating layer and within the contact opening. A stress buffer layer is deposited overlying the barrier layer wherein the stress buffer layer prevents volcano defects. A tungsten plug is formed within the contact opening to complete the formation of the tungsten plug metallization without volcano defects in the fabrication of an integrated circuit device.

Abstract: A method for substantially improving the electrical characteristics of contact surfaces in contact holes and via holes that are formed in semiconductor substrates is disclosed. The method involves, in particular, the introduction of an "after-etch" process, subsequent to the application of prior art methods of "main-etch," "over-etch," and "soft-etch" that are employed in opening holes in semiconductors, in general. The said process uses an isotropic dry etch assisted by argon gas ions in such a way that the area of the contact surfaces are increased manyfold through the formation of three-dimensional structures. It is shown that the resulting electrical contact resistance of the surfaces is reduced, and therefore, improved substantially.

Abstract: A new method of controlling the critical dimension width of polysilicon by using a disposable hard mask is described. A semiconductor substrate is provided wherein the surface of the substrate has an uneven topography. A layer of polysilicon is deposited over the uneven surface of the substrate. The polysilicon layer is covered with a spin-on-glass layer wherein the spin-on-glass material planarizes the surface of the underlying topography. A semiconductor layer is deposited over the surface of the planarization layer to act as a hard mask wherein the semiconductor layer is opaque to actinic light. The semiconductor layer is covered with a uniform thickness layer of photoresist. The photoresist layer is exposed to actinic light wherein the semiconductor layer prevents reflection of the actinic light from its surface. The photoresist layer is developed and patterned to form the desired photoresist mask for the polysilicon layer.

Abstract: Microlenses are formed on a solid state imager comprising a substrate having planar radiation-sensitive regions and upstanding electrode regions by forming a conformal layer of a first, low refractive index material on the substrate, and forming a planarized layer of a second, higher refractive index material on top of the layer of first material. The portions of the second material extending down between the upstanding electrode regions act as microlenses deflecting light which would otherwise fall on the radiation-insensitive electrode regions on to the radiation-sensitive regions, thus improving the quantum efficiency of the imager.

Abstract: A process for fabricating a tantalum nitride diffusion barrier for the advanced copper metallization of semiconductor devices is disclosed. The process comprises the steps of first preparing a semiconductor device fabricated over the surface of a silicon substrate having a component with a fabricated contact opening. Before the formation of the copper contact by deposition, the process performs a tantalum nitride low-pressure chemical-vapor-deposition procedure that deposits a layer of tantalum nitride thin film over the surface of the device substrate. After the copper deposition, a photoresist layer is subsequently fabricated for patterning the deposited copper contact and tantalum nitride layers, whereby the deposited thin film of tantalum nitride is patterned to form the thin film as the metallization diffusion barrier for the semiconductor device.

Abstract: A process is provided for making a tantalum capacitor chip which includes a tantalum chip body as well as an anode wire partially inserted into and partially projecting from the chip body. The process comprises the steps of compacting an initial divided amount of tantalum powder into an initial mass portion which is dimensionally smaller than the chip body, and compacting at least one additional divided amount of tantalum powder with the initial mass portion into the chip body. The capacitor chip thus obtained may be enclosed in a resin package to provide a surface mounting type tantalum capacitor.

Abstract: A new method of forming improved buried contact junctions is described. A first layer of polysilicon is deposited overlying a gate silicon oxide layer on a semiconductor substrate. These layers are etched away to provide an opening to the semiconductor substrate where the planned buried contact junction will be formed. A second polysilicon layer is deposited overlying the first polysilicon layer and the planned buried contact junction. Dopant is driven in from the second polysilicon layer to form the buried contact junction. The second polysilicon layer is etched away to provide a polysilicon contact overlying the buried contact junction and providing an opening to the semiconductor substrate where a planned source/drain region will be formed adjacent to the buried contact junction wherein a portion of the second polysilicon layer remains as residue. The residue is etched away whereby a trench is etched into the substrate at the junction of the planned source/drain region and the buried contact junction.

Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an amorphous nitride barrier layer (e.g. Ti--Si--N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the amorphous nitride layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The amorphous nitride barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.

Abstract: This invention describes a nanometer scale interband lateral resonant tunneling transistor, and the method for producing the same, with lateral geometry, good fanout properties and suitable for incorporation into large-scale integrated circuits. The transistor is of a single gate design and operation is based on resonant tunneling processes in narrow-gap nanostructures which are highly responsive to quantum phenomena. Such quantum-effect devices can have very high density, operate at much higher temperatures and are capable of driving other devices.

Abstract: A method and apparatus for depositing a film on a substrate by plasma-enhanced chemical vapor deposition at temperatures substantially lower than conventional thermal CVD temperatures comprises placing a substrate within a reaction chamber and exciting a first gas upstream of the substrate to generate activated radicals of the first gas. The substrate is rotated within the deposition chamber to create a pumping action which draws the gas mixture of first gas radicals to the substrate surface. A second gas is supplied proximate the substrate to mix with the activated radicals of the first gas and the mixture produces a surface reaction at the substrate to deposit a film. The pumping action draws the gas mixture down to the substrate surface in a laminar flow to reduce recirculation and radical recombination such that a sufficient amount of radicals are available at the substrate surface to take part in the surface reaction.

Abstract: A first insulating film is formed on the surface of a silicon substrate, and a first silicide wiring layer is deposited on the insulating film. A first mark is formed by transferring the pattern of a first reticle formed on the silicide wiring layer. A second insulation film is deposited on the mark and the first insulation film, and a second mark is formed on the first mark by transferring the pattern of a second reticle formed on the second insulation film. A second silicide wiring layer is deposited in the second mark and on the second insulating film. An anti dust deposit and a third mark are formed by transferring the pattern of a third reticle formed on the second silicide wiring layer. Thus, dusts from the marks produced by transferring the reticle inspection marks of the reticles can be effectively prevented to improve the yield of LSIs.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a silicon oxide film having a thickness of 5 nm or less on a silicon substrate or polysilicon film with a solution exhibiting an oxidation effect, forming a metal film on the silicon oxide film, and forming a silicide layer on the upper surface of the silicon substrate or polysilicon film by performing predetermined heat treatment.