Abstract: A surface of a compound semiconductor having at least gallium (Ga) and nitride (N) forms a target for sputtering with inert gas, so that oxide and other attachments are removed therefrom. The sputtering the surface is carried out until a disruption layer is formed which has atomically disordered and bumpy arrangement. Following the sputtering process, metal deposition by sputtering and alloying are carried out under vacuum in the same chamber used for the sputtering processes. As a result, the contact resistance between the surface layer and the deposited electrode layer is decreased.

Abstract: A method for forming a wiring layer for a semiconductor device is disclosed. During the formation of a VLSI-scale device having a contact hole with a large aspect ratio, metal layers are filled into the contact hole without spatial discontinuities, and a first wiring metal deposition process is carried out by applying a chemical vapor deposition (CVD) process. Compared with a conventional method, even if a thin film of aluminum is deposited, the wiring metal film can be deposited into the contact hole without spatial discontinuities. The upper opening of the contact hole may remain wide after deposition of the first wiring layer, and the wiring metal atoms may easily move into the contact hole upon reaching the wafer during a second wiring metal deposition. The disclosed invention may provide for superior wiring metal filling characteristics as compared with conventional methods.

Abstract: This invention describes a nanometer scale interband lateral resonant tunneling transistor, and the method for producing the same, with lateral geometry, good fanout properties and suitable for incorporation into large-scale integrated circuits. The transistor is of a single gate design and operation is based on resonant tunneling processes in narrow-gap nanostructures which are highly responsive to quantum phenomena. Such quantum-effect devices can have very high density, operate at much higher temperatures and are capable of driving other devices.

Abstract: A method for forming a contact between a conductive layer and a portion of the substrate during manufacture of a semiconductor device is disclosed. The process includes the steps of: (a) covering a semiconductor substrate with an insulating layer, and forming a contact hole on the portion where a contact is to be formed; (b) forming a metal layer on the whole surface of the substrate, and implanting positive ions into the metal layer; and (c) heat-treating the whole substrate so as to form a silicide layer. The metals used are those which can react with silicon to form a silicide, and may be selected from high melting point metals including Co, Ti, Ta, Ni, Mo, and Hf. The ions used are ions including H+ or halogen element ions, and a heat treatment is carried out so that the implanted positive ions may spread on/in the grain boundaries, or that the positive ions may bond with dangling bonds.

Abstract: A method of fabricating a gate having a barrier layer of titanium silicide is comprised of the steps of forming a layer of gate oxide. The gate oxide may be formed using a standard LOCOS process. A layer of doped polysilicon is deposited over the layer of gate oxide. A layer of titanium silicide is formed in a predetermined relationship with respect the layer of doped polysilicon, i.e., it may be deposited on top of the polysilicon or formed in a top surface of the polysilicon layer. A layer of tungsten silicide is deposited on top of the layer of titanium silicide. The layers of gate oxide, doped polysilicon, titanium silicide, and tungsten silicide are etched to form the gate. A gate thus fabricated is also disclosed.

Abstract: A method of forming electromigration resistant integrated circuit runners is disclosed. A collimated beam of particles is directed toward a substrate to form a metal nucleating layer. Then a non-collimated beam is used to form the rest of the metal layer. Then the layers are patterned to form runners.

Abstract: This invention relates to a composite electrode material for use in high rgy and high power density electrochemical capacitors, and to the electrochemical capacitor containing the electrodes. The electrodes are comprised of materials with high specific capacitance and electronic conductivity/high porosity. Specifically, the electrode is comprised of RuO.sub.2.xH.sub.2 O powder and carbon black or carbon fiber.

Abstract: A method of fabricating a metal line includes the steps of preparing a semiconductor substrate, depositing a first metal on the semiconductor substrate, heat-treating the first metal to form a first metal nitride layer, depositing a second metal on the first metal nitride layer, heat treating the second metal, depositing a third metal on the second metal, and heat treating both the third metal and the second metal to form a metal insulating layer in which the second and the third metals are mixed. The method of fabricating increases the area occupied by the metal line in a contact hole, decreases contact resistance, and increases the speed of the device.

Abstract: A MOS transistor employing a titanium-carbon-nitride (TiCN) gate electrode is provided. The MOS transistor has a gate insulating film, a gate electrode, and a source/drain region on a semiconductor substrate. The gate electrode is formed of a single TiCN film or a double film having a TiCN film and a low-resistant metal film formed thereon. The TiCN gate electrode exhibits a low resistance of about 80-100 .mu..OMEGA.-cm and can control variations in Fermi energy level.

Abstract: A method for forming an interconnect for making a temporary or permanent electrical connection to a semiconductor dice is provided. The interconnect includes a rigid substrate on which an insulating layer and a pattern of conductors are formed. A compliant layer is formed on the insulating layer of a material such as polyimide. Vias are formed in the compliant layer with metal contacts in electrical communication with the conductors. Microbumps are formed on the compliant layer in electrical communication with the contacts and are adapted to flex with the compliant layer. The interconnect can be used to provide a temporary electrical connection for testing bare semiconductor dice. Alternately the interconnect can be used for flip chip mounting dice for fabricating multi chip modules and other electronic devices.

Abstract: A method and apparatus for depositing material to conformally cover or fill holes within the surface of a semiconductor substrate. The preferred method includes the steps of coherently depositing a first thickness of the material onto the surface of the substrate; reverse sputtering the deposited material so as to coat the sidewalls of the contact holes with the deposited material; after the first thickness of the material is deposited onto the surface of the substrate, depositing a second thickness of the material onto the surface of the substrate; and while depositing the second thickness of the material onto the surface of the substrate, heating the substrate to enhance reflow of the material being deposited.

Abstract: A method of processing a substrate, such as a semiconductor wafer, in a vacuum processing chamber includes the steps of depositing a material on a surface of the substrate using a gas mixture, and purging the chamber of residual gases by flowing SiH.sub.4 into the chamber. Preferably, WSi.sub.x is deposited on a semiconductor wafer using a mixture comprising WF.sub.6, dichlorosilane and a noble gas, and the chamber is subsequently purged of residual WF.sub.6 and dichlorosilane by flowing SiH.sub.4 into the chamber. A further method of processing a substrate in a vacuum processing chamber includes the step of conditioning the chamber by flowing SiH.sub.4 into the chamber prior to depositing a material on the surface of the substrate. Semiconductor wafers processed according to the inventive method are characterized by more uniform sheet resistance values and reduced film stress.

Abstract: A multilayer structure having an oxygen or dopant diffusion barrier fabricated of an electrically conductive, thermally stable material of refractory metal-silicon-nitrogen which is resistant to oxidation, prevents out-diffusion of dopants from silicon and has a wide process window wherein the refractory metal is selected from Ta, W, Nb, V, Ti, Zr, Hf, Cr and Mo.

Abstract: In a method for producing a semiconductor device disclosed herein, a titanium film (131) is formed on a silicon layer and a titanium disilicide film (134) of a C49 structure is formed by the first rapid thermal annealing, followed by removing a titanium nitride film (132). The titanium disilicide film (134) thus formed is then subjected to phase transition to form titanium disilicide film (135a) of a C54 structure, and the titanium-excess titanium silicide film (133) is selectively removed by the second wet etching.

Abstract: Pulsed laser beams are applied to an object to be measured. A first laser beam of a pulsed laser beam having a first wavelength which is oscillated immediately after the rise of the pulsed laser beam, and a second laser beam having a second wavelength which is oscillated thereafter are used. Based on a difference between an intensity of first interfered light of reflected light of the first laser beam or transmitted light thereof, and an intensity of reflected light of the second laser beam or transmitted light thereof, temperatures of the object to be measured, and whether the temperatures are on increase or on decrease are judged. The method and device can be realized by simple structures and can measure a direction of changes of the physical quantities.

Abstract: A method of forming a silicon-based thin film for burying contact holes having a high aspect ratio is disclosed. The method comprises the steps of forming contact holes in an insulating film provided on a semiconductor substrate, and growing a silicon-based (silicon or silicon alloys) film containing impurities by Chemical Vapor Deposition to bury the contact holes. The growth is performed by simultaneously feeding a material gas for forming the silicon-based film and an etching gas for etching the silicon-based film, where the material gas is fed under surface reaction limiting conditions to equalize gas concentrations inside and outside said contact holes, and the etching gas is fed under supply rate limiting conditions to make the gas concentration outside the contact hole higher than that at the bottom of the contact hole.

Abstract: A method for producing aluminum electrolytic capacitors by inserting a pair of lead wires extended from an end surface of a capacitor body into through holes provided in an insulation board, by bending the pair of lead wires to fit uniformly in the grooves formed on the bottom surface of the insulation board, and by cutting projected portions of the pair of lead wires projecting from the brim face of the insulation board.

Abstract: A solid electrolyte capacitor comprises a capacitor element disposed in a case, and a rubber seal member tightly fitted in an upper opening of the case, with lead terminals projecting from the element and extending through the seal member. To fabricate the capacitor, a TCNQ complex salt is placed into a heating box and melted by heating. The capacitor element is placed into the box, impregnated with the complex salt, then immediately withdrawn from the box and cooled in air to solidify the salt by cooling. Subsequently, the lead terminals of the element are inserted through the seal member. The element is placed into the case which has approximately the same diameter as the heating box, with the seal member attached to the element, and the case is constricted to seal off its opening, whereby the solid electrolyte capacitor is obtained.

Abstract: The invention relates to an integrated circuit device comprising (i) a substrate; (ii) metallic circuit lines positioned on the substrate and (iii) a dielectric material positioned on the circuit lines. The dielectric material comprises the reaction product of a hyperbranched polymer and organic polysilica.

Abstract: A method and resulting structure for fabricating interconnects through an integrated circuit. The method includes adding more power lines 80, 100, 151 and/or increasing the width of power lines 120 and/or adding a power bus 140 near regions of high current flow. The resulting structure also provides more metallization near regions of high current flow. Similar to the method, the resulting structure may include additional power lines 80, 100, 151 and/or wider power lines 120 and/or a power bus 140 to increase the amount of metallization. An improved routing technique is also provided. Such routing technique includes providing an initial Ucs value and then adding additional lines near high current regions to decrease the Ucs value.