Abstract: A method and apparatus for depositing a film on a substrate by plasma-enhanced chemical vapor deposition at temperatures substantially lower than conventional thermal CVD temperatures comprises placing a substrate within a reaction chamber and exciting a first gas upstream of the substrate to generate activated radicals of the first gas. The substrate is rotated within the deposition chamber to create a pumping action which draws the gas mixture of first gas radicals to the substrate surface. A second gas is supplied proximate the substrate to mix with the activated radicals of the first gas and the mixture produces a surface reaction at the substrate to deposit a film. The pumping action draws the gas mixture down to the substrate surface in a laminar flow to reduce recirculation and radical recombination such that a sufficient amount of radicals are available at the substrate surface to take part in the surface reaction.

Abstract: A conductive via structure establishes an electrical interconnection between two conductive layers in a semiconductor structure by connecting a first conductive layer on a semiconductor substrate to a second conductive layer by means of a conductive via structure extending through a non-conductive layer separating the two conductive layers. The non-conductive layer preferably includes a layer of spin-on-glass (SOG), and is provided with a via aperture therethrough. A conductive spacer, preferably of TiW, is fabricated within the via aperture in abutment with the walls of the via aperture. A second conductive layer is fabricated over the non-conductive layer, the conductive spacer, and within the via aperture, to establish the completed electrical interconnection. The via structure reduces out-gassing and chipping from the SOG layer, yet provides a low electrical resistance path between the two conductive layers.

Abstract: A process for forming aluminum interconnect structures has been developed, that concentrates on alleviating the effects of the poor step coverage of the interconnect metallization, that develops in areas where aluminum overlies tungsten filled contact holes. A high pressure treatment of the aluminum based metallization layer is performed at pressures in the range of 50 to 120 Mega-pascal, to improve the coverage of the aluminum based layer, specifically in seams or voids in the underlying tungsten plugs.

Abstract: The present invention provides a structure and a method of manufacturing a resistor in a semiconductor device and especially for a resistor in an ink jet print head. The method begins by providing a substrate 10 having a field oxide region 20 surrounding an active area. The field oxide region 20 has an ink well region 52. Also a transistor is provided in the active area. The transistor comprises a source 12, drain 14 and gate electrode 16 18 19. A dielectric layer 24 is formed over the field oxide region 20 and the transistor 12 14 16 18. The dielectric layer 24 has contact openings over the source 12 and drain 14. A resistive layer 26 27 is formed over the dielectric layer 24 and contacting the source 12 and drain 14. The resistive layer 26 27 is preferably comprised of two layers of: a Titanium layer 26 under a titanium nitride 27 or a titanium layer 26 under a tungsten nitride layer 27. A first metal layer 28 is formed over the resistive layer.

Abstract: A semiconductor device includes an inter-level insulating film formed on a semiconductor substrate, wiring layers formed at positions having different depths inside the inter-level insulating film, open aperture portions having different depths and formed in the inter-level insulating film so as to reach each of the wiring layer, a titanium nitride film (first conductor layer) formed on the inner surface of each of the open aperture portions and on the inter-level insulating film, a silicon oxide film (insulating film) formed on the titanium nitride film other than the titanium nitride film formed on the inner surface of each of the open aperture portions, a tungsten film (second conductor layer) formed inside each of the open aperture portions, and an aluminum wiring (third conductor layer) formed on the tungsten film.

Abstract: A chip-formed solid electrolytic capacitor having a structure wherein a projecting anode lead is not provided for an anode member. The solid electrolytic capacitor is fabricated by the following manner: First, an electrically insulating resin such as a fluororesin is impregnated into an end face of a porous electrode member to form an insulating resin impregnated portion, and an electrode lead member is bonded to the anode member at the insulating resin impregnated portion. An anodic oxidation film, a solid electrolyte layer and a cathode layer successively are formed on the anode member. Then, an electrically insulating outer package is applied so that the cathode layer on a face of the anode member opposing to the face on which the electrode lead member is mounted is exposed.

Abstract: An etch stop layer prevents damage to the underlying semiconductor material or metallization layer during etching of a dielectric layer overlying the etch stop layer. The etch stop layer, aluminum nitride or aluminum oxide is used underlying silicon dioxide to prevent damage to the semiconductor material during a fluorocarbon based etch of the silicon dioxide. The etch stop layer is also used underlying a silicon dioxide layer and overlying a titanium nitride or titanium tungsten layer used in metallization to prevent etching of the titanium nitride or titanium tungsten layer during etching of the silicon dioxide.

Abstract: A method of forming conductive wiring on a semiconductor substrate. A plurality of contact holes having different sizes are formed in an insulating film formed on the substrate. A first barrier metal layer is formed on the insulating film, and a tungsten layer is uniformly formed on the first barrier metal layer. The tungsten layer is etched back to form plug-shaped tungsten regions in small contact holes and tapered tungsten regions in large contact holes. The central area of the first barrier metal layer in the large contact hole is exposed. A second barrier metal layer is formed covering the plug-shaped tungsten region and the tapered tungsten region and the exposed first barrier metal layer and sandwiching the plug-shaped and tapered tungsten regions between the first and second barrier metal layers, preventing punch-through of Al atoms from an Al layer to be thereafter formed, into the substrate, even when the first barrier metal layer is damaged during etch-back.

Abstract: A method is described for forming a high contact resistance region within the drain region or source region of an insulated gate field effect transistor as part of a high resistance resistor for electrostatic discharge protection of the field effect transistor. The silicide free contact region is formed as part of a self aligned silicide, or salicide, contact process. Nitrogen ion implantation followed by annealing is used to form a silicon nitride mask at the silicide free contact region. The mask prevents the formation of low contact resistance metal silicide at the silicide free contact region during the salicide process. Low resistance contacts to the gate electrode, source, and drain are formed using metal silicide.

Abstract: After forming a contact hole in an insulator layer, which is formed on a substrate covering an impurity doped region, a Ti film, a TiN film (or TiON film), and an Al alloy (for example, an alloy of Al--Si--Cu) layer are sputtered (consecutively from the bottom level) for forming a wiring material layer. A wiring layer is formed by patterning the wiring material layer in accordance with a wiring pattern. Portions with a 0% coverage of the Al alloy layer are eliminated by sputtering the Al alloy layer with a substrate temperature in a range between 100.degree.and 150.degree. C.

Abstract: A unique photoresist process is provided which achieves clean and complete lift-off of a thin film layer such as a sputtered thin film formed on a photoresist which is formed above a semiconductor substrate. The process of the present invention relies on a reentrant photoresist profile which breaks the continuity of the thin film layer. Accordingly, the process of the present invention ensures a clean lift-off. The desired photoresist profile which breaks the continuity of the thin film layer can be obtained by a typical photoresist process preceded by an oxidation process that takes place on the surface of the semiconductor substrate. The oxidation process provides a thin native oxide layer with thickness ranging from about 30 to 50 .ANG.. No extra processing steps involving dielectric film deposition and etch are required to achieve clean lift-off. Nevertheless, the process of the present invention ensures the clean lift-off of the thin film layer.

Abstract: A wiring layer formed on a field insulating film covering the surface of a semiconductor substrate is covered with an interlayer film. The interlayer film is covered with a flat film such as spin-on-glass formed by spin coating. The flat film has, for example, a laminated structure of an organic SOG film and an inorganic SOG film. The inorganic SOG film is suitable for obtaining a polishing speed generally equal to that of a CVD oxide film. The insulating film and the flat film are chemical-mechanical polished at a same polishing speed until the flat film is thoroughly removed, to leave a planarized insulating film.

Abstract: A defect free intermetal dielectric, IMD, and method of forming the defect free IMD are described. The IMD uses spacers formed by means of etchback of a layer of spin-on-glass, SOG. In order to use an oxide layer formed by means of plasma enhanced tetra-ethyl-ortho-silicate, PE-TEOS, as part of the IMD an oxide cap layer formed using plasma enhanced chemical vapor deposition, PE-CVD, is used to isolate the SOG spacers from the PE-TEOS formed oxide layer. By isolating the PE-TEOS formed oxide layer from the SOG spacers a reliable and defect free IMD is achieved.

Abstract: A system and method for reducing the contact resistance associated with tungsten plug contacts to P-doped diffusion regions of a semiconductor device. Before or during the formation of the tungsten plug contacts, a high energy, low dosage of an N-dopant or neutral species such as silicon or germanium is implanted into the P-doped diffusion regions of the semiconductor device. The implantation causes lattice damage within the P-doped diffusion regions, enhancing diffusion of the P-dopant within the P-doped diffusion regions. This results in the P-dopant diffusing toward the contact, replacing dopant lost to segregation into the contact metalization, and thus reducing the contact resistance.

Abstract: Disclosed is a novel contact structure comprising an underlying layer of titanium silicide, an intermediate layer of titanium boride, and an overlying layer of polysilicon. Also disclosed is a method for forming the contact structure which comprises depositing a titanium layer in the bottom of a contact opening having oxide insulation sidewalls, forming an overlying layer of polysilicon above the titanium layer, and annealing the two layers together. The resulting contact structure is formed with fewer steps than contact structures of the prior art and without the need for additional steps to achieve uniform sidewall coverage, due to high adhesion of the overlying layer of polysilicon with oxide insulation sidewalls of the contact opening. The contact structure has low contact resistance, and provides a suitable diffusion barrier due to a high melting point.

Abstract: A method of forming a guard ring for a Schottky diode is comprised of the steps of forming anode and cathode contact openings. A layer of doped material is deposited and etched to create spacers in the anode and cathode openings. The outdiffusion of dopant from the spacers is controlled to form a guard ring in the well without affecting the active area. The method can be used to create a p-type guard ring in an n-well or an n-type guard ring in a p-well. A Schottky diode constructed according to the method is also disclosed.

Abstract: A method of forming a silicon oxide film by setting a silicon wafer in a chamber capable of introducing oxidizing gas and being evacuated and by heating the silicon wafer in an oxidizing atmosphere. The method includes the steps of: transporting the silicon wafer into the chamber without contacting the silicon wafer with air; introducing an ozone containing gas into the chamber and setting the interior of the chamber to a predetermined pressure; and heating the silicon wafer to a predetermined temperature and oxidizing the surface of the silicon wafer. The predetermined pressure is preferably between 200 Torr and 0.1 Torr. Ozone may be generated from oxygen by applying ultraviolet rays to the upper space of a silicon wafer. The temperature of ozone to be introduced is preferably low. It is preferable to incorporate infrared heating in order not to excessively heat ozone and to heat a silicon wafer to a high temperature.

Abstract: A process of making a capacitor element for a solid electrolytic capacitor is provided which comprises the steps of preparing at least one capacitor piece which includes a chip of a sintered mass of metal powder and an anode wire projecting from the chip, forming a dielectric layer on the chip, forming a solid electrolyte layer on the chip, forming a metal layer on the chip, and cutting the metal wire at a position spaced from the chip. A water-repellent member is fitted on the anode wire and located close to the chip at least up to finishing the step of forming the solid electrolyte layer. Further, the water-repellent member is shifted along the anode wire away from the chip at least before cutting the anode wire, whereas the anode wire is cut at a position between the chip and the shifted water-repellent member.

Abstract: A method for eliminating plasma-induced charging damage during manufacture of an integrated circuit is described. A semiconductor substrate having a first conductivity type is provided. An oxide layer is formed on the semiconductor substrate. An opening is formed in the oxide layer. A polysilicon layer is formed over the oxide layer and in the opening. A diffusion region is formed in the semiconductor substrate, connected to the polysilicon layer through the opening, having a second conductivity type opposite to the first conductivity type, whereby a buried contact is formed. The buried contact is connected, through the substrate, to a ground reference. Further processing in a plasma environment is performed that would normally produce charging damage to the integrated circuit, but whereby the buried contact prevents the charging damage.

Abstract: A method for packaging an integrated circuit begins by providing an organic substrate (310) having at least one device site (312). Within each device site, one or more electronic devices (532) is mounted. Around the device site, slots (316) and corner holes (318) are formed. In one embodiment, a negative feature, such as a notch (326), is formed in the substrate along the inner edge (315) of the slots. After the electronic device is mounted and encapsulated in a plastic package body (320), the device is excised from the substrate by punching corner regions of a final package perimeter (317). The placement of the slots, corner holes, and notches results in a punch periphery that is free from burrs, provides maximum active interconnect area, and minimizes surface and/or edge damage during the punch operation. Instead of forming notches, a positive feature, such as a protrusion (426) can be incorporated into a punching tool segment (428) to provide the same benefits.