Abstract: Provided are an information processing apparatus and a power-off control method of an information processing apparatus. An information processing apparatus includes a nonvolatile memory; a cache memory for caching data to be written into the nonvolatile memory; a power switch; a spatial change detecting section configured to detect a change in state of a space around the power switch; a notification section configured to send a user a notification; and a control section. The control section is configured to determine an action of a user likely to turn the power switch off, based on a detection signal outputted by the spatial change detecting section; operate the notification section to send a user a notification that the action is being performed, in response to recognizing the action; and write data stored in the cache memory into the nonvolatile memory after operating the notification section to send the user the notification.

Abstract: An electronic device and method in which a tuning process is performed during memory initialization, so as to reduce the occurrence of data read errors. The device may include a clock generator that generates a clock signal transmitted to a memory device, and a host control module that transmits to the memory device a change signal changing at least a portion of the clock signal, and/or a tuning related command. The host control module may receive setting data from the memory device, corresponding to at least one of the change signal and the tuning related command.

Abstract: A user profile layer provides a benefit to a user by allowing access to user profile setting and data across multiple information handling systems running one or more operating systems. Operating system specific data may be stored in a user profile operating system layer while user data may be stored in a user profile data layer. Each time a user logs in to an information handling system, a layering driver captures changes to user data and to user settings corresponding to the operating system. A new user profile operating system layer is created for each type of operating system associated with a user while only one user profile data layer is maintained for the same user. In this way, any changes made to the same operating system data or user data are captured by the user's specific user profile and usable each time the user logs in to any information handling system.

Abstract: A scheduler is presented that can adjust, responsive to a thermal condition at the processing device, a scheduling of process threads for compute units of the processing device so as to increase resource contentions between the process threads.

Abstract: An electronic device may include a transducer configured to generate an electrical output responsive to an input, and a data storage element configured to change state responsive to the transducer. The electronic device may include a power circuit configured to turn on and supply power responsive to the data storage element changing state, and a processing circuit configured to be powered by the power circuit.

Abstract: A multi-host power controller (MHPC) of a flash-memory-based storage device is disclosed. In one aspect, the MHPC receives power mode change requests from each of multiple input/output (I/O) clients. The MHPC extracts and stores a “vote,” or a requested power mode, from the power mode change requests, and then applies a voting logic to the stored votes to determine whether to transition the flash-memory-based storage device between power modes. If the flash-memory-based storage device is not currently operating in the power mode determined by the MHPC, the MHPC is configured to issue a power mode change command to the flash-memory-based storage device to transition to the determined power mode. In this manner, the MHPC is able to control the power mode of the flash-memory-based storage device while receiving direct power mode change requests from multiple I/O clients.

Abstract: A method and system for applying a system change in an automated fashion and verifying the correct operation of a computing device after the system change includes allowing the computing device an opportunity to at least temporarily apply the system change, determine whether the system change is successful, and discard the system change if not successful, using operating system and BIOS components.

Abstract: A system on chip is provided. The system on chip includes a first memory to store a plurality of encryption keys, a second memory, a third memory to store an encryption key setting value, and a CPU to decrypt encrypted data which is stored in an external non-volatile memory using an encryption key corresponding to the encryption key setting value from among the plurality of encryption keys, to store the decrypted data in the second memory, and to perform a boot using data stored in the second memory. Accordingly, security of a boot operation can be improved.

Abstract: A method for power management comprises registering and subscribing one or more endpoint devices to a remote power management service. The one or more endpoint devices are connected with a local network. Power state information of the one or more endpoint devices is obtained. Power state of one or more endpoint devices is changed using the remote power management service.

Abstract: A dispatch module implemented in at least one of a memory or a processing device is operatively coupled to a first processing module and a second processing module. The first processing module has a priority higher than a priority of the second processing module. The dispatch module includes a workload counter associated with the first processing module to provide an indication of a workload at the first processing module. The dispatch module initiates a clock signal at the second processing module only if the indication of the workload at the first processing module satisfies a criterion. The dispatch module sends a data unit to the second processing module for processing only if the indication of the workload at the first processing module satisfies a criterion.

Abstract: A mechanism for automatically enrolling option ROMs into the system security database used for a UEFI Secure Boot is discussed. A request is received by a computing device to auto-enroll one or more option ROMs for one or more respective devices on the next boot of the system. Upon receiving the request, a flag or other type of indicator indicative of an auto-enroll status is changed to an active mode. The indicator is stored in non-volatile memory and may be stored as a UEFI Authenticated Variable. Following the changing of the indicator, the system is either reset or shut down. During the next boot only, after identifying the indicator indicative of an active mode auto-enroll status, the signatures for the option ROMs of all discovered devices whose signatures do not exist in the system security database are calculated (hashed) and added to the UEFI Secure Boot database without user interaction.

Abstract: A method or system comprises reading content of a plurality of system files from storage media of a storage device, generating a master storage device system file, and storing the master storage device system file on the storage media at a master system file location. The location of the master system file is provided to boot firmware or hardware. As a result, when the system boots up, the master system file is read into a temporary cache.

Abstract: A power detection circuit includes a sense element to convey current from a source to a load, a compensating reference element located proximate to the sense element, a comparator, and a precision current sink. The comparator includes a first input coupled to the sense element, a second input coupled to the compensating reference element, and an output. The comparator is configured to assert a signal on the output in response detecting that a first voltage on the first input equals a second voltage on the second input. The precision current sink is coupled to the second input of the comparator and is configured to pull constant current through the compensating reference element based on a predetermined power threshold.

Abstract: The subject disclosure is directed towards protecting code in memory from being modified after boot, such as code used in a dedicated microprocessor or microcontroller. Hardware, such as in logic or in a memory protection unit, allows a range of memory to be made non-writeable after being loaded, e.g., via a secure boot load operation. Further, startup code that is used to configure the hardware/memory may be made non-executable after having run once, so that no further execution may occur in that space, e.g., as a result of an attack. A function in the runtime code may allow for a limited, attack-protected reconfiguration of sub-regions of memory regions during the runtime execution.

Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power control logic to receive power capability information from a plurality of devices to couple to the processor and allocate a platform power budget to the devices, set a first power level for the devices at which the corresponding device is allocated to be powered, communicate the first power level to the devices, and dynamically reduce a first power to be allocated to a first device and increase a second power to be allocated to a second device responsive to a request from the second device for a higher power level. Other embodiments are described and claimed.

Abstract: An apparatus includes voltage summation logic to provide a summed voltage corresponding to a sum of voltage contributions, each contribution associated with a corresponding port controller of a plurality of port controllers. The apparatus also includes a first port controller to determine, based on the summed voltage, whether a second power source is to be coupled to a system power bus of a system via a second port controller of the plurality of port controllers, and if not, the first port controller is to couple a first power source to the system power bus. Other embodiments are described and claimed.

Abstract: In an embodiment, a method includes identifying a core of a multicore processor to which an incoming packet that is received in a packet buffer is to be directed, and if the core is powered down, transmitting a first message to cause the core to be powered up prior to arrival of the incoming packet at a head of the packet buffer. Other embodiments are described and claimed.

Abstract: A position aligning apparatus of a vehicle installed at a bottom surface of a vehicle inspection line to respectively correspond to both sides of a front wheel and both sides of a rear wheel of the vehicle so as to target-position the vehicle at an inspection position includes: a front aligning unit regulating a front movement of the vehicle having entered into the vehicle inspection line and aligning a front right/left position of the vehicle while pressing a front wheel of the vehicle in a right/left direction according to operation of a first actuator; a rear aligning unit aligning a rear right/left position of the vehicle while pressing a rear wheel of the vehicle in the right/left direction according to operation of a second actuator; and a controller controlling the operation of the first and second actuators.

Abstract: Implementations of the present disclosure involve a system and/or method for implementing a reset controller of a microprocessor or other type of computing system by connecting the reset controller to a reset controller bus or other type of general purpose bus. Through the reset bus, the reset controller signals used to generate the reset sequence of the system may be transmitted to the components of the system through a bus, rather than utilizing a direct wire connection between the components and the reset controller. The wires that comprise the reset bus may then be run to one or more components of the microprocessor design that are restarted during the reset sequence. Each of these components may also include a reset controller circuit that is designed to receive the reset control signals from the reset controller and decode the signals to determine if the received signal applies to the component.

Abstract: A method and system for adjusting bandwidth within a portable computing device based on danger signals monitored from one on more elements of the portable computing device are disclosed. A danger level of an unacceptable deadline miss (“UDM”) element of the portable computing device may be determined with a danger level sensor within the UDM element. Next, a quality of service (“QoS”) controller may adjust a magnitude for one or more danger levels received based on the UDM element type that generated the danger level and based on a potential fault condition type associated with the particular danger level. The danger levels received from one UDM element may be mapped to at least one of another UDM element and a non-UDM element. A quality of service policy for each UDM element and non-UDM element may be mapped in accordance with the danger levels.