Abstract: Systems and methods for securely passing user authentication data between a Pre-Boot Authentication (PBA) environment and an Operating System (OS) are described. In some embodiments, an Information Handling System (IHS) may include a processor; and a Basic I/O System (BIOS) coupled to the processor, the BIOS having program instructions stored thereon that, upon execution by the processor, cause the computer system to: identify an encrypted Single-Sign-On (SSO) token and a Trusted Platform Module (TPM) key pair provisioned by an Operating System (OS) and stored in an OS registry; extract a TPM public key from the TPM key pair; encrypt a PBA private key generated by a PBA application with the TPM public key; and store the encrypted PBA private key, the TPM key pair, and the encrypted SSO token in a shadow partition of a self-encrypting hard drive coupled to the IHS.

Abstract: A method, system, and computer program product for controlling power supplied to a processor is disclosed. A voltage regulator is set to a first voltage regulator set point, wherein the first voltage regulator set point provides a first load line for operation of the processor. A change in an operation of the processor from a first operating condition along the first load line to a second operating condition along the first load line is determined. The voltage regulator is the set to a second voltage regulator set point and the processor is operated at a third operating condition on a second load line corresponding to the second voltage regulator set point.

Abstract: An information processing device, includes: a storage to store a program to be booted; a central processing unit to start a plurality of booting programs and read the program stored in the storage using a virtual address; a main memory to store the program based on a read instruction of the program; and a controller, including an address translator that translates a virtual address into a physical address, to read the program from the storage according to the read instruction, and write the read program in a plurality of discontinuous areas of the main memory on the physical address, wherein the central processing unit executes a start module which sets a virtual address space in the central processing unit and the controller before the plurality of booting programs are booted, and reads the written program from the main memory using the virtual address which is designated by the reading instruction.

Abstract: A computer system includes plural servers in which virtual machines are arranged; plural power supply apparatuses that supply electric power to the servers; and a control apparatus that controls arrangement of the virtual machines in the servers. The control apparatus solves an integer programming problem whose objective function is total power consumption by the servers and by the power supply apparatuses, the total power consumption being described as a function of the arrangement of the virtual machines; and arranges the virtual machines based on a solution of the integer programming problem.

Abstract: A method of proactively event triggering in a computer system is disclosed. The computer system includes an application unit and an interface. The method includes the application unit sending a setting signal to change a voltage level of a pin of a control chip module; the pin generating a triggering event to the interface unit when the voltage level of the pin changes; and the interface accessing a controller according to the triggering event to allow the application unit to communicate with the controller proactively.

Abstract: A system on chip is provided. The system on chip includes a first memory to store a plurality of encryption keys, a second memory, a third memory to store an encryption key setting value, and a CPU to decrypt encrypted data which is stored in an external non-volatile memory using an encryption key corresponding to the encryption key setting value from among the plurality of encryption keys, to store the decrypted data in the second memory, and to perform a boot using data stored in the second memory. Accordingly, security of a boot operation can be improved.

Abstract: A controlled apparatus periodically transmits state information indicating the state of the apparatus, and when the state has been changed, transmits state information indicating the state after the change. Upon receiving state information from the controlled apparatus, a control apparatus, when not requesting a change of state in the controlled apparatus, returns the state information to the controlled apparatus, and when requesting a change of the state in the controlled apparatus, changes state parameters in the state information that correspond to the state to be changed to required values and transmits the state information after the change to the controlled apparatus as a control command. The controlled apparatus, upon receiving the control command from the control apparatus, changes to a state in accordance with the state parameters that follow the change and transmits the state information indicating the state after the change to the control apparatus.

Abstract: A method and corresponding apparatus for aligning a data signal with a corresponding clock signal include oversampling the data signal based on the corresponding clock signal and generating corresponding data samples. An indication of skew between the data signal and the corresponding clock signal is detected based on data samples. A variable delay line coupled to the data signal is then adjusted based on the indication of skew detected. According to at least one example implementation, the data signal is oversampled based on the corresponding clock signal and multiple time-shifted versions of the corresponding clock signal. At least one signal of the corresponding clock signal and the multiple time-shifted versions of the corresponding clock signal is employed in sampling the data signal at a potential transition edge of the data signal.

Abstract: A method provides processor initialization in different platform environments via a single code set. The method includes: in response to detecting a power-on operation of the processor, a microcontroller retrieving hardware procedures (HWP) framework code from a storage and triggering execution of the HWP framework code on the processor. The execution of the HWP framework code generates a HWP framework that comprises a plurality of application programming interfaces (APIs) which govern how all communication processes involving hardware procedures can be accomplished. The method further includes performing one or more initialization procedures by communicating one or more attribute data via the HWP framework to configure the processor for operation within a specific platform environment in which the processor is to be operated. The HWP framework includes standard interfaces and enables direct updates to hardware procedures without requiring a new flash code or a firmware patch.

Abstract: Durations of power management states are predicted on a per-process basis. Some embodiments include storing, in one or more data structures associated with one or more processes, information indicating previous durations of a power management state associated with the process(es). Some embodiments also include predicting a subsequent duration of the power management state for the process(es) using information stored in the data structure(s).

Abstract: A system and computer program product provide processor initialization in different platform environments via a single code set. The system includes: in response to detecting a power-on operation of the processor, a microcontroller retrieving hardware procedures (HWP) framework code from a storage and triggering execution of the HWP framework code on the processor. The execution of the HWP framework code generates a HWP framework that comprises a plurality of application programming interfaces (APIs) which govern how all communication processes involving hardware procedures can be accomplished. The system further includes the microcontroller performing one or more initialization procedures by communicating one or more attribute data via the HWP framework to configure the processor for operation within a specific platform environment in which the processor is to be operated.

Abstract: Input power quality for a processing device is sensed. In response to detection of poor power quality, input power is disconnected, and the processing device backs up its machine state in non-volatile logic element arrays using available stored charge. When power is restored, the stored machine state is restored from the non-volatile logic element arrays to the volatile logic elements whereby the processing device resumes its process from the state immediately prior to power loss allowing seamless processing across intermittent power supply.

Abstract: Methods and apparatus for implementing Power over Ethernet (PoE) for auxiliary power in computer systems. Under aspects of the methods, one or more voltage inputs comprising standard power input is employed by a power control component in a network interface in an apparatus such as a network adaptor board, a System on a Chip (SoC), computer server or server blade to supply power to a network controller on the apparatus when the apparatus is operating at a normal power state. To enable the apparatus to maintain network communication when operating at a reduced power state, a PoE power input derived from at least one PoE signal received at at least one Ethernet jack of the apparatus is employed to provide power to the network controller absent use or availability of the standard power input. Accordingly, the PoE power input facilitates an auxiliary power function that may be used alone or in combination with existing (as applicable) auxiliary power input when apparatus are operated in reduced power states.

Abstract: A data processing method during a boot procedure of a smart device is provided. The data processing method includes: when a data request is detected during the boot procedure of the smart device, looking up whether a page cache pre-storing a small data file required for booting includes requested data of the data request, the small data file being file having a data amount smaller than a predetermined threshold; when the page cache includes the requested data, determining whether the data request is a data reading request or a data writing request; when the data request is the data reading request, duplicating the requested from the page cache to a system memory according to the data request. A boot time can be reduced through the above method.

Abstract: Embodiments of the invention provide adaptive power ramp control (APRC) in microprocessors. One implementation of the APRC can compute a present core power and a present power ramp condition in the microprocessor, for example, to determine whether the present power is in a particular predefined control zone and whether the present power ramp is greater than a predefined threshold for that control zone. Those determinations can indicate a likelihood of an imminent, undesirable power ramp condition and can inform entry into a control mode. The APRC can generate an appropriate stall control signal in response to its present control mode, and the stall control signal can stall operation of at least one functional unit of the microprocessor according to a predefined stall pattern. This can effectively combat the imminent power ramp condition by reducing the power usage of the microprocessor.

Abstract: Methods, systems, and devices are described for configuration of multiple power distribution units (PDUs) in an efficient manner. Power distribution units may be discovered on a network, and automatically configured according to a configuration defined for a particular location. A location may be, for example, a geographical region, a data center, a zone within a data center, a cabinet, or an individual PDU. All PDUs associated with a particular location may be provided with a common configuration file that defines operating parameters for the PDUs. In such a manner, a user may simply connect the PDU to the network, with the appropriate configuration provided without additional involvement of the user.

Abstract: A system on chip (SoC) includes a plurality of function circuits including a plurality of logic circuits and a plurality of function circuits each of which includes a logic circuit and a memory, and a plurality of power path controllers respectively coupled to a plurality of first power sources at first input terminals, commonly coupled to a second power source at second input terminals, and respectively coupled to the memories at output terminals. The logic circuits are respectively coupled to the first power sources, and configured to be supplied with a plurality of first power supply voltages from the first power sources, respectively. Each of the memories is configured to be selectively supplied, by a corresponding one of the power path controllers, with one of a corresponding one of the first power supply voltages from a corresponding one of the first power sources and a second power supply voltage from the second power source.

Abstract: The invention relates to an electronic device that includes a wake-up system that operates at a substantially low power level and is applied to wake up the electronic device from a sleep mode. The wake-up system comprises a sound transducer that converts a received sound signal to an electrical signal and a keyword detection logic that preliminarily identifies a speech energy profile that corresponds to at least one of a plurality of keywords in a part of the electrical signal. In some embodiments, a keyword finder is further activated to identify with an enhanced accuracy whether the at least one keyword exists in the part of the electrical signal, and generates a wake-up control to activate a host of the electronic device from its sleep mode.

Abstract: There is provided a memory control apparatus including a deciding unit deciding, among a first main storage apparatus that is a main storage apparatus with low power consumption and a second main storage apparatus with power consumption higher than the power consumption of the first main storage apparatus as memory devices of multiple CPU cores, whether the second main storage apparatus is capable of being suspended, and a power managing unit suppressing a power supplied to the second main storage apparatus and at least one of the multiple CPU cores in a case where the deciding unit decides that the second main storage apparatus is capable of being suspended.

Abstract: A method of operating a system on chip (SoC) includes determining to switch from a selected low-power core among a plurality of low-power cores to a high-performance core among a plurality of high-performance cores, counting the number of high-performance cores that are operating among a plurality of high-performance cores, determining a maximum operating frequency of the plurality of high-performance cores based on the counted number, and switching from the selected low-power core to the selected high-performance core based on the determined maximum operating frequency.