Abstract: A method comprising may include storing, in a BIOS comprising a program of instructions executable by the processor and configured to cause the processor to initialize one or more information handling resources of an information handling system, a hardware profile of the information handling system, the hardware profile comprising identifying information of one or more information handling resources of the information handling system recorded during creation of the hardware profile. The method may also include, during a boot of the information handling system in a hardware verification mode, creating a new hardware profile comprising identifying information of the one or more information handling resources, comparing the new hardware profile to the hardware profile stored in the BIOS, and if the new hardware profile differs from the hardware profile stored in the BIOS, issuing an alert indicating potential tampering with hardware of the information handling system after creation of the profile.

Abstract: A power supply control circuit for controlling power supply or stop of power supply is provided between a power source and a circuit block such as a processor. The power supply control circuit not only performs power supply to the circuit block or intentionally stops power supply but also is able to hold the power supply potential when the power supply is suddenly stopped, so that a loss of data in the circuit block can be prevented. By utilizing the power supply potential held by the power supply control circuit, data in the circuit block is saved in the nonvolatile memory device, so that a loss of data in the circuit block can be prevented. As described above, the power supply control circuit functions as a power gating switch and a circuit for holding the power supply potential in the case where power supply is suddenly stopped.

Abstract: A central processing unit with dual boot capabilities is disclosed comprising an instruction memory further comprising a first and second memory area which are configured to be individually programmable, wherein first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory, respectively. The instruction set for the central processing unit comprises a dedicated instruction that allows to perform a swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the dedicated instruction in the active memory followed by a program flow change instruction in the active memory, whereupon the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory.

Abstract: Power gating decisions can be made based on measures of cache dirtiness. Analyzer logic can selectively power gate a component of a processor system based on a cache dirtiness of one or more caches associated with the component. The analyzer logic may power gate the component when the cache dirtiness exceeds a threshold and may maintains the component in an idle state when the cache dirtiness does not exceed the threshold. Idle time prediction logic may be used to predict a duration of an idle time of the component. The analyzer logic may then selectively power gates the component based on the cache dirtiness and the predicted idle time.

Abstract: Methods and systems for platform configuration management may use a platform configuration register (PCR) stored on a trusted platform module (TPM) included with an information handling system. A basic input/output system (BIOS) may include instructions to generate a first PCR value based on BIOS settings while a user is operating the BIOS. When the first PCR value indicates a change from a previous PCR value stored in the PCR, an alert may be displayed to the user and sent to a network administrator. The BIOS may display an indication of a mapping of BIOS settings to the first PCR value.

Abstract: A method and an apparatus for controlling a sleep mode in a portable terminal having a main controller and a sub-controller operating at low power are provided. The method includes detecting, by the sub-controller, a first sensor signal generated by a first sensor when the main controller is in the sleep mode, extracting a sensed pattern from the detected first sensor signal, determining whether the extracted sensed pattern is substantially identical with a preset wake-up pattern, and cancelling the sleep mode by waking-up the main controller when the extracted sensed pattern is substantially identical with the wake-up pattern.

Abstract: A laser processing program creation device sets an evaluation region in an adjacent plane to a target plane; calculates the position of the extremity of the product profile in the axial direction within the evaluation region; sets a first line segment passing through the position of the extremity and extending orthogonally to the axis in the target plane; locates a processing area in the range surrounded by the first line segment, a second line segment, and the product profile, the second line segment extending in the axial direction from an end of the first line segment to the product profile; allocates a trajectory for laser beam cutting to form a notch or a hole in the processing area; and allocates a trajectory for laser beam cutting to cut the material along the product profile.

Abstract: In an approach to allowing a computer to boot from a user trusted device (UTD), the computer comprises a data storage device storing operating system (OS) services, and a version of an OS loader. The UTD is connectable to the computer and stores a boot loader, detectable by a firmware executing at the computer, and an OS loader, and wherein the UTD prevents an unauthenticated user to modify the boot loader and the OS loader stored thereon. The computer then, upon connection, lets the boot loader be detected by the firmware for execution of the boot loader at least partly at the computer, to cause to transfer the OS loader from the UTD to the computer, and executes the transferred OS loader at least partly from the computer, to execute at least one crypto driver for the OS, to start the OS services and complete booting of the computer.

Abstract: A thermostat may include one or more temperature sensors, a processor configured to operate in a sleep mode and a wake mode, and a Wi-Fi chip that wirelessly communicates with a thermostat management server. The Wi-Fi chip may be configured to receive data packets from the thermostat management server while the processor operates in the sleep mode, and determine a priority level of the received data packets. The priority level may include a standard priority level and a keep-alive priority level. The Wi-Fi chip may also be configured to filter the received data packets based on the determined priority level of each packet such that the keep-alive priority level packets are discarded, and forward the standard priority level packets to the processor.

Abstract: An integrated circuit including a universal monitor system includes a detector circuit. The detector circuit includes a start trigger circuit receiving first signals, an end trigger circuit receiving second signals, and a latency circuit coupled to outputs of the start and end trigger circuits. The start trigger circuit detects a start event from the first signals. The end trigger circuit detects an end event from the second signals. The detector circuit further includes: a data trigger circuit receiving third signals and detecting transferred data therefrom; a first counter circuit coupled to the latency circuit and calculating a total latency; a second counter circuit coupled to at least one of the start trigger circuit and counting start events, or the end trigger circuit and counting end events; and a third counter circuit coupled to an output of the data trigger circuit and counting a total amount of data transferred.

Abstract: An apparatus including: an input interface configured to enable user configuration of a future time window; and a report interface configured to produce a report relating to a first sub-set of a plurality of active timers that expire at programmed future points in time, wherein the first sub-set of the plurality of active timers expire during the user-configured future time window.

Abstract: Some embodiments relate to a method of using a network to control a power management system. The method includes using the network to access a generator controller that is part of the power management system. The method further includes using the network to exchange communications with the generator controller in order to permit the generator controller to control other electronic components that are part of the power management system.

Abstract: This invention relates to methods and devices for clock synchronization. The invention has particular application in the alignment of slave clocks to a master clock and in dealing with transmission delay asymmetries where the forward and reverse communication paths between the master and slave clocks have asymmetric transmission rates. Such methods and devices have particular application in small cell backhaul solutions for 4G/LTE deployments. In embodiments of the invention, the slave clock uses link rate information to estimate the transmission delay asymmetry and thus estimate the offset and skew of the slave clock. Embodiments provide a simple linear approximation technique and a Kalman filter-based technique for estimating offset and skew of the slave clock.

Abstract: A method for arranging joints to a 3D model is present. The method first obtains a 3D file, and executes a slice process to a 3D model recorded in the 3D file for obtaining a plurality of cross sections. During the slice process, the method determines if differences between each two cross-section areas of two adjoined cross sections is larger than a threshold. If the difference between the two cross-section areas of two adjoined cross sections is larger than the threshold, the method obtains a corresponding joint data from a database, and arranges the joint data into a position between the two adjoined cross sections. The method finally outputs the arranged 3D model to a 3D printer.

Abstract: Reducing standby power of an information apparatus is described. In one aspect, a laptop PC is equipped with an Ethernet controller. The laptop PC operates in an intermittent manner and a DC/DC converter supplies power to the Ethernet controller. The laptop PC determines whether the Ethernet controller is connected to a network by a cable in a time Twake during which the converter is on. When it is determined that the Ethernet controller is connected, the laptop PC maintains operation of the DC/DC converter until the Ethernet controller is disconnected. When it is determined that the Ethernet controller is not connected, the laptop PC stops operation of the DC/DC converter during a time Tsleep and resumes the operation thereof when a setting time by a timer elapses. The DC/DC converter supplies power to the Ethernet controller when it is actually connected to the network. Other aspects are described.

Abstract: A communication device receives at least a portion of a packet. Power is reduced to a subset of components of a communication device. The subset of components for which power is reduced is determined based, at least in part, on a length of the packet. The power is reduced for a time period based, at least in part, on the length of the packet.

Abstract: Individual first ones of a plurality of non-volatile logic element arrays are designated to restore first in response to entering a wakeup or restoration mode. These non-volatile logic element arrays include instructions for an order in which other non-volatile logic element arrays are to be restored next. So configured, the processing device can be set to have one or more NVL arrays restored first, which arrays are pre-configured to guide further wakeup of the device through directed restoration from particular NVL arrays. Certain NVL arrays can be skipped if the functions stored therein are not needed, and the order of restoration of others can be tailored to a particular wakeup time and power concern through restoration in parallel, serial, or combinations thereof.

Abstract: A Serial Peripheral Interface (SPI) controller is provided for use within a computer system. The SPI controller includes a clock that generates system clock signals that synchronize a data transfer operation, and a dynamic clock delay element that phase shifts the clock signals with a delay offset and outputs read data that was received during a read operation from an SPI slave device with the clock signals that were phase shifted.

Abstract: A provisioning server delivers operating systems to more than one virtual machine in different subnetworks. Since one provisioning server can be used for multiple subnetworks, this reduces the need to build, license, and support a provisioning server or a provisioning server farm for each subnetwork. This eliminates additional Infrastructure Software licensing; reduces additional effort to implement and maintain more provisioning servers; increases flexibility to add additional subnetworks; and scales a provisioning server farm to meet demand by adding servers.

Abstract: In an embodiment, a system includes a power management unit (PMU), a non-volatile memory, a volatile memory, and a processor. The PMU may be configured to generate a power supply voltage, change a state of a status signal responsive to an event, and reduce a voltage level of the power supply voltage responsive to a predetermined period of time elapsing from detecting the event. The system may be configured to transition from a first to a second operating mode responsive to the change of the state of the status signal, and cancel pending commands to the non-volatile memory responsive to the transition to the second operating mode. The non-volatile memory may be configured to complete active commands prior the predetermined period of time elapsing.