Abstract: A non-volatile memory system comprises an integrated memory assembly in communication with a memory controller. The integrated memory assembly includes a memory die bonded to a control die. The control die includes one or more control circuits for controlling the operation of the memory die. The control circuits are configured to receive a request to copy data on the memory die, read codewords on the memory die in response to the request, decode the codewords to identify errors in the codewords, correcting the errors in the codewords, and program the codewords back into the memory die. In one embodiment, the codewords read are stored in the memory die as single bit per memory cell data and the codewords programmed back into the memory die after correcting errors are programmed as multiple bit per memory cell data.

Abstract: A memory system includes a memory module and a memory controller. The memory module includes data chips that store data and are assigned to a first sub-channel that generates a first code word or a second sub-channel that generates a second code word, where the first code word and the second code are used to fill a single cache line. The memory controller, upon detection of a hard-fail data chip among the data chips, copies data from the hard-fail data chip to the ECC chip, releases mapping between the hard-fail data chip and corresponding I/O, and defines new mapping between the ECC chip and the corresponding I/O pins.

Abstract: Disclosed herein is an apparatus that includes a first group including a plurality of first latch circuits coupled in series and a second group including a plurality of second latch circuits coupled in series. Each of the first latch circuits performs a latch operation in synchronization with a rise trigger signal. Each of the second latch circuits performs a latch operation in synchronization with a fall trigger signal. The rise and fall trigger signals are alternately activated every even clock cycles or every odd clock cycles. In response to a division ratio, first one or more of the first and second latch circuits are bypassed and second one or more of the first and second latch circuits are cyclically coupled.

Abstract: A substrate for a medical device, a portion of which is brought into contact with or inserted into a subject. The substrate includes a patient circuit conductively connected to the portion that is configured to be brought into contact with or inserted into the subject, and a ground-side circuit configured to perform at least one of transmission of a signal, reception of a signal, and supply of electric power on the patient circuit. The ground-side circuit is grounded by a protective ground to ensure safety of a manipulator of the medical device. The substrate also includes an insulating layer between the patient circuit and the ground-side circuit providing insulation between the patient circuit and the ground-side circuit, and an isolated circuit provided apart from the patient circuit and the ground-side circuit on the insulating layer and having a different reference potential from the patient circuit and the ground-side circuit.

Abstract: Methods, systems, and devices for shared error correction coding (ECC) circuitry are described. For example, a memory device configured with shared ECC circuitry may be configured to receive data at the shared circuitry from either a host device or a set of memory cells of the memory device. The shared circuitry may be configured to generate a set of multiple syndromes associated with a cyclic error correction code, based on the received data. As part of an encoding process, an encoder circuit may generate a set of parity bits based on the generated syndromes. As part of a decoding process, a decoder circuit may generate an error vector for decoding the received data, based on the generated syndromes. The decoder circuit may also correct one or more errors in the received data based on generating the error vector.

Abstract: A method for detecting a reading error of a datum in memory. A binary word which is representative of the datum and an error correcting or detecting code is read by: reading a first part of the binary word stored at a first address in a first memory circuit; and reading a second part of the binary word stored at a second address in a second memory circuit. The first and second parts read from the first and second memory circuits, respectively, are concatenated to form a read binary word. The datum is then obtained by removing the error correcting or detecting code from the read binary word. A new error correcting or detecting code is calculated from the obtained datum and compared to the removed error correcting or detecting code to detect error in the obtained datum.

Abstract: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.

Abstract: Various implementations described herein relate to systems and methods for detecting address corruption when using a memory device to store and retrieve data, including but not limited to, reading combined information from a memory device, determining encoded data by de-combining address information from the combined information, and detecting address corruption by decoding the encoded data.

Abstract: A medical apparatus includes a trocar, a control handle, a first electrical wire, and a second electrical wire. The trocar is used for insertion into an organ of a patient, and includes (i) a cannula having a longitudinal axis, (ii) a position sensor that is fitted inside the cannula, and (iii) a camera that is coupled to a movable element, which is fitted inside the cannula and configured to be moved along the longitudinal axis for moving the camera along the cannula. The control handle is coupled to a proximal end of the movable element and is configured to move the movable element and the camera. The first electrical wire is coupled between the control handle and the camera. The second electrical wire is coupled between the control handle and the position sensor, and has a slack configured to compensate for a motion of the camera.

Abstract: A system for improving radiation tolerance of memory senses an amount of radiation exposure and, based on the sensed amount of radiation exposure, determines whether to perform one or more techniques for mitigating the effects of the radiation exposure. As an example, the system may perform a data refresh operation by re-writing data that has been corrupted by radiation, or the system may adjust the reference voltage used to read memory cells. In another example, the system may perform a fault repair operation by re-programming cells that have erroneously transitioned from a program state to an erase state. The system may selectively perform different radiation-mitigation techniques in a tiered approach based on the sensed amount of radiation in order to limit the adverse effects of the more invasive techniques.

Abstract: A method, apparatus, and system for facilitating bending of an instrument in a surgical or medical robotic environment are provided. In one aspect, a surgical system includes an instrument comprising an end effector, the instrument capable of articulation via a bending section. The bending section includes a body including a first strut and a second strut, and a channel formed through the body. The first strut and the second strut form a gap therebetween, wherein the gap is in communication with the channel formed through the body.

Abstract: Methods, systems, and devices for power regulation for memory systems are described. In one example, a memory system, such as a memory module, may include a substrate, and an input/output component coupled with the substrate and operable to communicate signals with a host system. The memory system may also include one or more memory devices coupled with the substrate and the input/output component and operable to store data for the host system. A memory device of the one or more memory devices may include a power management component in its package with one or more memory dies. The power management component may be coupled with the one or more memory dies, and feedback component, and may be operable to provide one or more supply voltages for the one or more memory dies based on one or more voltages associated with the memory system.

Abstract: A medical system and an operating method of a medical system are disclosed. The medical system can operate an endoscope to perform an operation task with respect to a site of interest of an organ of concern in response to input from an operator. The medical system includes a controller that can record a model of the organ of concern generated during preoperative planning, and record the names of a plurality of sites in the organ of concern, and corresponding regions or points in the model with respect to a first coordinate system. The controller receives the name of the site of interest, and the operation task; associates the first coordinate system of the model with a second coordinate system of a display space displayed by a display image; and operates the endoscope with respect to the site of interest on the basis of the operation task.

Abstract: A detection system is adapted to perform methods for detecting defects in medical devices, during a reprocessing procedure, for example. The detection system may utilize computer-implemented instructions to determine the presence and nature of the defects, whether biological or mechanical, for example. The computer-implemented instructions may be adapted to include artificial intelligence and/or machine learning algorithms, and to process image data from digital inspection camera systems or proprietary camera systems. Upon identification of a defect present in a medical device, the detection system may notify users of the presence of the defect, as well as provide further recommended action to be taken regarding the medical device, if desirable, reducing potential instrument failure, patient injury or death. The disclosed detection system may be integrated into existing disinfection and sterilization systems currently used in medical facilities, such as hospitals and surgery centers, for example.

Abstract: A system includes a memory array of sub-blocks, each sub-block including groups of memory cells, and a processing device. The processing device causes a first wordline to be programmed through the sub-blocks with a mask by causing to be programmed, to a first voltage level: a first group of memory cells of a first sub-block; and a second group of memory cells of a second sub-block. The processing device further scans a second wordline that has been programmed and is coupled to the first wordline, scanning includes: causing a custom wordline voltage to be applied to the second wordline, the custom wordline voltage to select groups of memory cells corresponding to those of the first wordline programmed to the first voltage level; concurrently reading data from the selected groups of memory cells of the second wordline; and performing, using the data, an error check of the second wordline.

Abstract: A monotonic counter stores N binary words representing a value in N memory cells. When i memory cells of consecutive ranks between k modulo N and k+i modulo N each represent a value complementary to a null value, the counter is incremented by erasing a value of a memory cell of rank k+i+1 modulo N. When i+1 memory cells of consecutive ranks between k+1 modulo N and k+i+1 modulo N each represent the value complementary to the null value, the counter is incremented by incrementing a value of a memory cell of rank k modulo N by two step sizes and storing a result in a memory cell of rank k+1 modulo N, wherein, N is an integer greater than or equal to five, k is an integer, and i is an integer between 2 and N?3.

Abstract: A semiconductor memory device capable of suppressing an increase in power consumption and avoiding data destruction due to the row hammer problem is provided. The semiconductor memory device includes a refresh control unit (first control unit) that sets a memory cell refresh interval based on information about a memory cell refresh interval included in a predetermined command input from the outside.

Abstract: In accordance with one embodiment, an automated probe system includes a probe configured to be reversibly inserted into a live body part, a robotic arm attached to the probe and configured to manipulate the probe, a first sensor configured to track movement of the probe during an insertion and a reinsertion of the probe in the live body part, a second sensor configured to track movement of the live body part, and a controller configured to calculate an insertion path of the probe in the live body part based on the tracked movement of the probe during the insertion, and calculate a reinsertion path of the probe based on the calculated insertion path while compensating for the tracked movement of the live body part, and send control commands to the robotic arm to reinsert the probe in the live body part according to the calculated reinsertion path.

Abstract: An electronic device includes a command generation circuit configured to generate a refresh command and a driving control signal, which are enabled during an all-bank refresh operation, according to a logic level combination of an internal chip selection signal and an internal command address. The electronic device also includes a buffer control circuit configured to generate, from the refresh command and the driving control signal, a first buffer enable signal for enabling a first group of buffers and a second buffer enable signal for enabling a second group of buffers.

Abstract: An integrated circuit includes a plurality of memory cells, a first pair of complementary data lines, and a second pair of complementary data lines. The plurality of memory cells include a first array of memory cells and a second array of memory cells. The first pair of complementary data lines are coupled to the first array of memory cells. The second pair of complementary data lines are different from the first pair of complementary data lines and are coupled to the second array of memory cells. A number of memory cells in the first array of memory cells is different from a number of memory cells in the second array of memory cells.