Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.

Abstract: To ameliorate the detrimental effects of time delays, techniques and systems are disclosed for detecting time delays in a plant, facility, or environment (such as a power system) controlled by an NCS, and for providing more resilient control capabilities for adapting to the detected time delays. A time delay estimate can be determined by comparing the expected state of the plant, calculated from a plant model, with the state of the plant described by its telemetry data. Techniques for adapting to a time delay include: switching to an emergency controller and acting in accordance with a local reference model; sending adjusted control commands in accordance with an expected plant state; and instructing a transmitter to transmit subsequent communications packets over multiple redundant communication channels.

Abstract: A system and method for Internet of Things (IoT) Implementations for controlling electronic equipment. One embodiment of a system includes: an IoT hub that includes a network interface to couple the IoT hub to an IoT service over a wide area network (WAN), and at least one IoT device communicatively coupled to the IoT hub over a wireless communication channel. The IoT device includes an infrared (IR) or radio frequency (RF) blaster to control environmental control equipment via IR or RF communication with the environmental control equipment, at least one sensor to measure current environmental conditions capable of being controlled by the environmental control equipment, the IoT device to transmit an indication of the current conditions to the IoT hub over the wireless communication channel; and the IoT hub includes a remote control code database to store remote control codes usable to control the environmental control equipment.

Abstract: Associative templates for machining operations and systems and methods including the same are disclosed herein. The methods include defining an electronic model for a feature and defining a tool path to be traveled by a cutting tool to form the feature. The methods further include recording an associative template as program code. The program code is configured to program an electronically controlled machine tool to automatically define the electronic model of the feature and to automatically define the tool path responsive to user selection of the program code on the electronically controlled machine tool. The electronically controlled machine tool further is configured to automatically form the feature within the workpiece responsive to executing the program code. The systems include electronically controlled machine tools including machine controllers that are programmed to execute the program code.

Abstract: A power converter for a computer device having a processing unit and a memory device is suggested. The power converter is connectable to the computer device by a coupling circuitry, wherein the computer device requires an actual input voltage. The power converter comprises a voltage regulator, a measuring entity, and a determining entity. The voltage regulator is configured to control an actual output voltage for the coupling circuitry based on a determined reference output voltage. The measuring entity is configured to measure an actual output current of the voltage regulator output to the coupling circuitry. The determining entity is configured to determine the determined reference output voltage such that the determined reference output voltage equals a sum of the actual input voltage of the computer device and the product of the measured actual output current and a resistance of the coupling circuitry.

Abstract: A computer system and a method for setting basic input/output system (BIOS) are disclosed. The computer system comprises a remote computer and servers. The remote computer transmits a setting command. Each of the servers comprises a first management unit and a motherboard. The motherboard comprises a storage device and a processor. The storage device stores the BIOS. The processor executes the BIOS. The processor communicates with the first management unit to determine whether the BIOS configuration needs to be updated after the server rebooted. The processor updates the BIOS according to the setting command when the BIOS configuration must to be updated.

Abstract: A mobile communication system and a method of providing content data to user of a vehicle using the communication system. The method includes: determining at a vehicle a last-used content data function associated with a previous ignition cycle, wherein the last-used content data function was used to provide content data to vehicle users; determining an adaptive boot sequence that includes the last-used content data function; executing the adaptive boot sequence at a subsequent ignition cycle which includes initiating the last-used content data function; and providing content data in the vehicle via the last-used content data function.

Abstract: A method for power management comprises registering and subscribing one or more endpoint devices to a remote power management service. The one or more endpoint devices are connected with a local network. Power state information of the one or more endpoint devices is obtained. Power state of one or more endpoint devices is changed using the remote power management service.

Abstract: In an embodiment, a method includes identifying a core of a multicore processor to which an incoming packet that is received in a packet buffer is to be directed, and if the core is powered down, transmitting a first message to cause the core to be powered up prior to arrival of the incoming packet at a head of the packet buffer. Other embodiments are described and claimed.

Abstract: A position aligning apparatus of a vehicle installed at a bottom surface of a vehicle inspection line to respectively correspond to both sides of a front wheel and both sides of a rear wheel of the vehicle so as to target-position the vehicle at an inspection position includes: a front aligning unit regulating a front movement of the vehicle having entered into the vehicle inspection line and aligning a front right/left position of the vehicle while pressing a front wheel of the vehicle in a right/left direction according to operation of a first actuator; a rear aligning unit aligning a rear right/left position of the vehicle while pressing a rear wheel of the vehicle in the right/left direction according to operation of a second actuator; and a controller controlling the operation of the first and second actuators.

Abstract: Power gating decisions can be made based on measures of cache dirtiness. Analyzer logic can selectively power gate a component of a processor system based on a cache dirtiness of one or more caches associated with the component. The analyzer logic may power gate the component when the cache dirtiness exceeds a threshold and may maintains the component in an idle state when the cache dirtiness does not exceed the threshold. Idle time prediction logic may be used to predict a duration of an idle time of the component. The analyzer logic may then selectively power gates the component based on the cache dirtiness and the predicted idle time.

Abstract: A method for arranging joints to a 3D model is present. The method first obtains a 3D file, and executes a slice process to a 3D model recorded in the 3D file for obtaining a plurality of cross sections. During the slice process, the method determines if differences between each two cross-section areas of two adjoined cross sections is larger than a threshold. If the difference between the two cross-section areas of two adjoined cross sections is larger than the threshold, the method obtains a corresponding joint data from a database, and arranges the joint data into a position between the two adjoined cross sections. The method finally outputs the arranged 3D model to a 3D printer.

Abstract: Reducing standby power of an information apparatus is described. In one aspect, a laptop PC is equipped with an Ethernet controller. The laptop PC operates in an intermittent manner and a DC/DC converter supplies power to the Ethernet controller. The laptop PC determines whether the Ethernet controller is connected to a network by a cable in a time Twake during which the converter is on. When it is determined that the Ethernet controller is connected, the laptop PC maintains operation of the DC/DC converter until the Ethernet controller is disconnected. When it is determined that the Ethernet controller is not connected, the laptop PC stops operation of the DC/DC converter during a time Tsleep and resumes the operation thereof when a setting time by a timer elapses. The DC/DC converter supplies power to the Ethernet controller when it is actually connected to the network. Other aspects are described.

Abstract: A communication device receives at least a portion of a packet. Power is reduced to a subset of components of a communication device. The subset of components for which power is reduced is determined based, at least in part, on a length of the packet. The power is reduced for a time period based, at least in part, on the length of the packet.

Abstract: A method for reducing power consumption in a communication device. The method includes determining, by the communication device, that a packet transmitted on a communication medium is not intended for the communication device and estimating a length of the packet. If the length is greater than a first threshold but less than a second threshold, selecting a first group of components of the communication device to which to reduce power. If the length is greater than the second threshold, selecting a second group of components of the communication device to which to reduce power. The second group of components includes the first group of components. The method includes reducing power to the selected group of components.

Abstract: A power management technique utilizing a method for accurately and rapidly estimating the change in the statistical distribution of data at each block in a communication system leading to or originating from a memory that is experiencing voltage scaling induced errors is disclosed. An appropriate memory supply voltage that maximizes power savings is found by exploiting the available SNR slack while keeping system performance within a required margin.

Abstract: A bus interface, for allowing a plurality of devices to communicate with one another via the bus, includes a bit timing symmetrization component for symmetrizing the bit stream. For an incoming bit stream, the bit timing symmetrization component further includes an input delay filter for delaying recessive to dominant edges for a given received bit stream and sampling the delayed input signal at the sample point. In one embodiment, bit timing synchronization may still be performed with the undelayed recessive to dominant edges. For an outgoing bit stream, the bit timing symmetrization component transmits a recessive bit, that followed a previously transmitted dominant bit, before the start of the next bit time, and transmits a dominant bit, that followed a previously transmitted recessive bit, with a delay of a configurable amount of time.

Abstract: According to an embodiment, an electronic device is configured to output extended display identification data (EDID) to another electronic device, and to receive image data corresponding to the EDID from the other electronic device. The electronic device includes a memory and a controller. The memory is configured to store therein a plurality of distinct types of EDID. The controller is configured to detect a condition of a power source supplied to the electronic device, and to select an EDID corresponding to the condition.

Abstract: Embodiments of the invention provide adaptive power ramp control (APRC) in microprocessors. One implementation of the APRC can compute a present core power and a present power ramp condition in the microprocessor, for example, to determine whether the present power is in a particular predefined control zone and whether the present power ramp is greater than a predefined threshold for that control zone. Those determinations can indicate a likelihood of an imminent, undesirable power ramp condition and can inform entry into a control mode. The APRC can generate an appropriate stall control signal in response to its present control mode, and the stall control signal can stall operation of at least one functional unit of the microprocessor according to a predefined stall pattern. This can effectively combat the imminent power ramp condition by reducing the power usage of the microprocessor.

Abstract: Hiding logical processors from an operating system (OS) of a computer is described. In an example, a method of hiding at least one logical processor in a computer having a plurality of logical processors includes: initializing the plurality of logical processors by executing a pre-boot routine in system firmware; identifying at least one logical processor of the plurality of logical processors to be hidden from an operating system (OS) of the computer to provide at least one hidden logical processor and at least one visible logical processor; placing each of the at least one hidden logical processor into a system management mode (SMM) by executing a park routine in the system firmware; and booting the OS of the computer to use the at least one visible logical processor.