Abstract: In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption.

Abstract: A technique for managing a boot process on a data storage system having multiple storage processors is disclosed. A first storage processor communicatively coupled to and directs a second storage processor to perform one or more boot sequences. Elapsed time and timeout variables and an empty set of boot states are provided. After sleeping for a predetermined time the elapsed time variable is incremented. If the boot state of the second processor is not successful, the technique determines if the current boot state is a new boot state, and if so, the new boot state is added to the set of boot states and the elapsed time value is reset. The timeout value is set equal to the user defined value. If the elapsed time is less than the timeout value, the technique loops back to the sleep state and continues thereon, else if greater that the timeout value, a failure is indicated.

Abstract: A system for adjusting core voltage of an integrated circuit to optimize power savings has a ring oscillator on the integrated circuit for providing a ring oscillator signal. The system also has compare logic on the integrated circuit configured to compare the ring oscillator signal with a clock signal from a clock external to the integrated circuit. The compare logic is configured to make a determination whether a frequency of the clock signal is within a predefined margin of a frequency of the ring oscillator and to adjust the core voltage of the integrated circuit based on the determination. Through such adjustments, the core voltage is lowered while ensuring that the core voltage does not reach a point that causes timing errors.

Abstract: A method for replacing or repairing a non hot swappable component according to one embodiment includes supplying power to a first motherboard partition, a first storage partition, a second motherboard partition, and a second storage partition concurrently. The first storage partition is accessed and utilized with the second motherboard partition. The power to the first motherboard partition s selectively severed, and a non hot swappable component that has failed is removed from the first motherboard partition and replaced with a functioning component. Power is restored to the first motherboard partition.

Abstract: Embodiments include methods, systems, and computer storage devices directed to identifying that a trusted boot mode (TBM) control bit is set in an input/output memory management unit (IOMMU) and configuring the IOMMU to block a DMA request received by the IOMMU from a peripheral in response to the identifying.

Abstract: The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC maybe set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC.

Abstract: The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC may be set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC.

Abstract: The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC may be set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC.

Abstract: The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC may be set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC.

Abstract: An information processing apparatus to which an external device is attachable includes an initialization unit configured to, when the information processing apparatus is activated from a power-off state, execute initialization of the external device, and not to, when the information processing apparatus is returned from a power-saving state, execute the initialization of the external device.

Abstract: An information processing apparatus compares a first device model information of the information processing apparatus with second device model information stored in a nonvolatile memory unit being externally connected to the information processing apparatus, and compares first device identification information of the information processing apparatus with second device identification information stored into the nonvolatile memory unit based on detection of a boot-up. When the device model information comparison process is determined to be identical and when the device identification information comparison process is determined to be non-identical, the information processing apparatus reads out second BIOS setup value stored in the nonvolatile memory unit and replaces with the first BIOS setup value stored in the BIOS information memory unit.

Abstract: A method is provided for resuming one or more cores of a multi-core processor that is part of an electronic device, the method comprising: grouping wakeup sources into a plurality of computing domains; receiving an interrupt associated with a wakeup source; identifying a first computing domain from the plurality that the wakeup source is part of; mapping the first computing domain to a first indication of one or more states of a first core of the processor; configuring the first core to enter the one or more states that are indicated by the first indication; and resuming the first core after the first core is configured.

Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.

Abstract: A sensing device includes: a sensor module that includes a group of sensors, at least one of which is set as a motion sensor, and can switch an operation mode to an overall operation mode in which all of the group of sensors operate and a partial operation mode in which a part of the sensors including the at least one sensor set as the motion sensor operate; and a control unit that controls the switching of the operation mode of the sensor module on the basis of an output from the motion sensor.

Abstract: A method, computer program product, and apparatus for managing power management in a data processing system are presented. A core is activated and configured to operate at a frequency in response to a request to increase a processing capacity. A determination whether a use of power resulting from activating the core meets a policy for the use of the power is made. A set of parameters is adjusted to meet the policy for the use of power in response to a determination that the use of power does not meet the policy. A determination whether a number of operations performed by a set of cores is made. An indication that the request to increase the processing capacity is unavailable is made in response to the number of operations having not increased.

Abstract: A storage apparatus that includes a power supply unit that supplies power to a controller when power supply from the outside to a storage apparatus stops, a surplus power determination unit that determines surplus power that is power, which is to be supplied by the power supply unit and by which power for the saving of data into a nonvolatile memory is exceeded, a target voltage determination unit that determines a first target voltage based on the surplus power, and a charging processing unit that carries out a charging process for the power supply unit with a first current value until the first target voltage reached and that carries out a charging process for the power supply unit with a second current value lower than the first current value until a second target voltage higher than the first target voltage is reached from the first target voltage.

Abstract: The present disclosure provides an electronic device having a USB interface and a method for starting USB communication with such an electronic device, so as to solve the problem of a risk of damaging a mobile phone terminal device arising from sharing of an interface by a charger and a USB communication cable in the related art. In the electronic device, a port GPIO of a baseband chip is connected to a pin USB_VBUS of a USB interface of the baseband chip; based on this circuit, a power management chip detects a state of plugging-in-or-pulling-out of the charger and generates a corresponding interrupt request; and the baseband chip controls the GPIO to output a corresponding level according to the interrupt request. By connecting the port GPIO and the pin USB_VBUS and controlling an output level of GPIO with a software, a high level or a low level (as a triggering signal for starting or terminating the USB communication) is input to the pin USB_VBUS, thus avoiding damage to the device.

Abstract: A method to reduce memory power consumption for a computing platform includes inspecting an operating parameter associated with a resource of the computing platform that is updated by the resource of the computing platform during runtime of the computing platform. Memory power utilization is then predicted for the computing platform during the runtime of the computing platform based at least in part on the operating parameter. A current power state of at least one memory module resident on the computing platform is transitioned to one of a plurality of power states based on the predicting of the memory power utilization.

Abstract: Techniques for mobile device power state are described. In one or more implementations, a mobile device includes a computing device that is flexibly coupled to an input device via a flexible hinge. Accordingly, the mobile device can operate in a variety of different power states based on a positional orientation of the computing device to an associated input device. In one or more implementations, an application that resides on a computing device can operate in different application states based on a positional orientation of the computing device to an associated input device. In one or more implementations, techniques discussed herein can differentiate between vibrations caused by touch input to a touch functionality, and other types of vibrations. Based on this differentiation, techniques can determine whether to transition between device power states.

Abstract: An uninterruptable power supply (UPS) system/method providing power line conditioning and power factor correction (PFC) that incorporates centralized battery backup energy storage architecture is disclosed. The system generally comprises an AC-DC power supply with active PFC (power factor correction) function, a battery transfer switch, an isolated battery charger placed between the utility power source and battery strings, battery strings connecting the battery charger and the battery transfer switch, EMI/Lightning circuitry that provides lighting/line surge protection as well noise suppression functions, and a controller monitoring the quality of the utility power source. Uninterruptable power for data centers is achieved in this context via use of the battery strings, battery transfer switch, battery charger, and controller system configuration. Disclosed methods associated with this system generally permit the UPS to operate in a distributed fashion in support of computing systems within data centers.