Abstract: An uninterruptable power supply (UPS) system/method providing power line conditioning and power factor correction (PFC) that incorporates centralized battery backup energy storage architecture is disclosed. The system generally comprises an AC-DC power supply with active PFC (power factor correction) function, a battery transfer switch, an isolated battery charger placed between the utility power source and battery strings, battery strings connecting the battery charger and the battery transfer switch, EMI/Lightning circuitry that provides lighting/line surge protection as well noise suppression functions, and a controller monitoring the quality of the utility power source. Uninterruptable power for data centers is achieved in this context via use of the battery strings, battery transfer switch, battery charger, and controller system configuration. Disclosed methods associated with this system generally permit the UPS to operate in a distributed fashion in support of computing systems within data centers.

Abstract: A display device is provided that may include a memory to store a boot screen data to be provided when booting the display device, an interface unit to receive the stored boot screen data and another boot screen data, and a processor to change the stored boot screen data into the other boot screen data that is received in the interface unit, and to control to outputting the boot screen data when booting according to a boot code that includes a command for outputting the boot screen data. A display unit may output the boot screen data according to control of the processor.

Abstract: In transferring data between a first computing device having a first clock generator component and a second computing device having a second clock generator component, timing information is generated by at least the first clock generator component and is shared over a communication channel with the second computing device to synchronize the first and second clock generator components. Upon detecting that power available to the first computing device has fallen below a designated threshold level, the first computing device enters a power loss mode. Upon entering the power loss mode, the first computing device selectively inactivates one or more designated components by a power module while continuing operation of at least the first clock generator component to maintain the synchronizing timing information associated with the second clock generator component.

Abstract: In one embodiment, the present invention includes a method for receiving an incoming packet in a packet buffer and associating it with a flow identifier. Based on the flow identifier, a core to which the incoming packet is to be directed may be determined, and a power management hint can be transmitted to cause the core to be powered up. Other embodiments are described and claimed.

Abstract: A data transmitting apparatus for processing data to be transmitted to a data receiving apparatus which reproduces received data stored in a received data storage unit, comprising: a signal processor for processing data; a transmitter for wirelessly transmitting the data processed in the signal processor to the data receiving apparatus; a signal processing controller for controlling the signal processor to operate intermittently; a clock/power controller for restricting a clock signal supply and/or power supply to the signal processing controller during a non-operating time period of the intermittent operation; and a wake-up controller for lifting the restriction put by the clock/power controller based on an amount of data stored in the received data storage unit.

Abstract: An overclocking module, a computer system and a method for overclocking are provided. The method is used to overclock the computer system. The overclocking module of the invention includes a timer, a monitoring unit and a control unit. The timer starts to count when the computer system is booted. The monitoring unit monitors whether the computer system performs a boot-up procedure within a period of time. The control unit adjusts an operating frequency of the computer system to overclock the computer system automatically according to the monitoring result of the monitoring unit.

Abstract: Aspects of a method and system for a connector with integrated power over Ethernet functionality are provided. In this regard, one or more circuits and/or processors that reside within and/or on a connector may be operable to manage a supply power that is delivered over a cable based on characteristics of the connector and/or characteristics of the cable. The cable may carry the supply power while concurrently carrying data communications. The one or more circuits and/or processors may be operable to source and sink the supply power. The one or more circuits and/or processors may be operable to control which one or more conductors of the cable are utilized for conveying the supply power.

Abstract: A memory controller includes an digitally programmable delay unit having a selectable delay time receiving a read-enable signal and outputting a delayed read-enable signal. The delay time is selected in response to an externally applied delay-control signal. A sampling unit in the memory controller outputs data received from a separate memory, in synchronization with the delayed enable signal. The delay time may be a multiple of the period of a clock signal.

Abstract: A reset controller is adopted which performs control for causing an external reset terminal to be shared for external output of a reset signal and input of a reset signal from outside, allowing a reset input from the external reset terminal in a state in which a power supply voltage is stable, and causing, when a reset factor due to turn-on of a power supply voltage or a reduction in the level of the power supply voltage is detected by a detection circuit, an input/output buffer to output a reset signal to the external reset terminal and masking the inflow of the reset signal from the input/output buffer to its input path, using a signal detected by the detection circuit. A mask period is assumed to be a period longer than a period from reset instructions to a reset release.

Abstract: A power supply apparatus of a computer system and a method for controlling a power sequence thereof are provided. The power supply apparatus includes a power sequence module, a voltage supply unit, and a state recording module. The power sequence module provides voltage enable signals in turn according to first power-good signals. The voltage supply unit provides power voltages in turn according to the voltage enable signals and returns second power-good signals. Components in the computer system also provide third power-good signals when the components receive the power voltages. When one of the third power-good signals is converted from enabled to disabled, the state recording module delays a tolerance period according to the component corresponding to the third power-good signal, and converts the first power-good signal corresponding to the third power-good signal from enabled to disabled after the tolerance period is delayed.

Abstract: A method for power management comprising inferring a user behavior from an action, inferring a mission state from the action and an event, forecasting a forecasted action from the user behavior and the mission state and outputting an instruction to modify a power resource allocation based on the forecasted action. A processor based assembly for power management of at least one device comprising a means to infer a user behavior from an action, a means to infer a mission state from the action and an event, a means to forecast and a means to plan power management from the inferred information. In some embodiments, the systems and methods apply pattern recognition algorithms and pattern learning algorithms to manage the power allocation to power consuming devices.

Abstract: In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption.

Abstract: In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption.

Abstract: Approaches for assessing information used in reverting to a prior BIOS version. A BIOS analyzes a file to determine whether the file may be used to revert the BIOS to a prior version of the BIOS. The file may contain a map of CMOS information.

Abstract: There is provided an apparatus including an information processing apparatus including an internal system which consumes electric power, an AC adaptor identification unit which identifies a rating of an AC adaptor connected, and a battery charge control unit which controls charge of a battery storing electric power, the electric power being used for operation of the internal system, where the AC adaptor identification unit identifies a rating of the AC adaptor connected and switches a power supply path to the battery charge control unit and/or the internal system into a proper state according to the identification results.

Abstract: The present invention discloses a switch device of a data card with a battery comprising a connection detecting module and a battery connection enable switch-off module inside an original battery power supply module. The present invention further discloses a method for saving power of a data card with a battery. Using the switch device of the data card and corresponding method for saving power of the data card, a switch button of the data card can be omitted and static power consumption of the battery can be avoided, thereby saving electric quantity of the battery.

Abstract: Disclosed is a microprocessor based system with a dynamically selectable Operating System that is capable of providing unique operating systems based upon current hardware states without user intervention. The system will determine the current state of the system and select from a plurality of operating systems the best operating system to load. In normal operating conditions the system will select the most full-featured and robust operating system. If, for example, the system loses alternating-current power, the system will shutdown, reboot, and automatically select an operating system with very limited capabilities and limited power consumption to allow the system to retrieve important data from the cache and store the data to a data storage device.

Abstract: To improve Wake-on-LAN (WOL) functionality of a device, a Media Access Control (MAC) address filtering function may be implemented in the device's Ethernet physical layer (ePHY) block. When the ePHY detects a WOL frame, the MAC filtering function in the ePHY may perform address comparison between the MAC address associated with the device, and the MAC address contained in the WOL frame. Performing the MAC address comparison within the ePHY allows the main system components, such as the main SOC and other components to remain in standby mode (or sleep mode) until a MAC address match has been determined. Therefore, the main system components do not need to be rebooted every time the device receives a WOL frame, only when there is a match between the MAC address of the system and the MAC address contained in the detected WOL packet.

Abstract: According to one embodiment, a server system includes a motherboard partition that includes a motherboard and at least one processor coupled to the motherboard, with each processor being coupled to a memory. The server system also includes a storage partition that includes the memory, and a power circuit being capable of supplying current to the motherboard partition and the storage partition independently, the power circuit including at least two redundant power supplies in parallel in the power circuit, with each redundant power supply being capable of providing an amount of current necessary to operate the server system, and the motherboard partition is adapted to run a server OS. In another embodiment, an active cluster system may include two server systems, with the motherboard partition from each server system being capable of communicating with the other server system's storage partition even if power is removed from the other system's motherboard partition.

Abstract: Resource-based adaptive server loading is described. In embodiments, a current load level can be determined for a resource that is utilized by an adaptive server system to process computer-executable instructions that are a dynamic computational demand on the adaptive server system. The current load level is compared with a target load level for the resource to establish a resource load level comparison. The adaptive server system can then be reconfigured, based on the resource load level comparison, to change the current load level on the resource for resource overload protection.