Abstract: An apparatus is disclosed that includes a processing sub-system having a plurality of processor circuits and an interrupt control circuit. The interrupt control circuit is configured to, in response to a peripheral interrupt, initiate performance of a task indicated by the peripheral interrupt by at least one of the plurality of processor circuits. The processing sub-system is configured to generate a power-down control signal in response to suspension of the plurality of processor circuits. A power management circuit disables power to the processing sub-system, including the interrupt control circuit, in response to the power-down control signal. The power management circuit enables power to the processing sub-system in response to a power-up control signal. The apparatus also includes a proxy interrupt control circuit configured to generate the power-up control signal in response to receiving a peripheral interrupt and power to the processing sub-system being disabled.

Abstract: Embodiments of the invention describe apparatuses, systems and methods to detect, during a host platform sleep state, a peripheral device audio jack plug being coupled to (e.g., inserted into) an audio jack connection socket. A specific sleep state of the host platform may be determined, and a system wake event may be generated so that the host platform wakes from the sleep state in response to the peripheral device being coupled to the audio jack connection socket. Thus, embodiments of the invention incorporated in handheld mobile computing devices such as smartphones and tablet computers with limited input/output (I/O) provide a user with alternative means for waking the device from a sleep state.

Abstract: Systems and methods for entry and exit latency reduction for low power states are described. In one embodiment, a computer implemented method initiates an energy-efficient low power state (e.g., deep sleep state) to reduce power consumption of a device. The method sets a power supply voltage that provides sufficient power to a dual power supply array for retention of states. Logic is powered down in this low power state.

Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.

Abstract: A system for baseboard management controller (BMC) operation is provided. The system includes a computing system including hardware on which an operating system is operable and sensors disposed to sense various attributes of the hardware and a BMC. The BMC is disposed in signal communication with the computing system and is bootable and operative independent of an execution of the operating system. Upon boot initialization of the BMC, the BMC includes an empty reserved database, issues to the computing system a query for a list of the sensors and builds and populates in the reserved database a sensor attribute repository in accordance with sensor data received from the computing system in response to the query and sensor attribute data associated with the sensor data.

Abstract: A method of dynamically controlling power within a multicore CPU is disclosed and may include receiving a degree of parallelism in a workload of a zeroth core and determining whether the degree of parallelism in the workload of the zeroth core is equal to a first wake condition. Further, the method may include determining a time duration for which the first wake condition is met when the degree of parallelism in the workload of the zeroth core is equal to the first wake condition and determining whether the time duration is equal to a first confirm wake condition. The method may also include invoking an operating system to power up a first core when the time duration is equal to the first confirm wake condition.

Abstract: A reset controller is adopted which performs control for causing an external reset terminal to be shared for external output of a reset signal and input of a reset signal from outside, allowing a reset input from the external reset terminal in a state in which a power supply voltage is stable, and causing, when a reset factor due to turn-on of a power supply voltage or a reduction in the level of the power supply voltage is detected by a detection circuit, an input/output buffer to output a reset signal to the external reset terminal and masking the inflow of the reset signal from the input/output buffer to its input path, using a signal detected by the detection circuit. A mask period is assumed to be a period longer than a period from reset instructions to a reset release.

Abstract: In certain aspects, a system for out-of-band configuring BIOS setting data (BIOSSD) includes a host computer and a service processor (SP). The SP stores a BIOSSD collection and a human interface data (HID) collection. The HID collection includes questions for data of the BIOSSD collection and corresponding options for each question. When a remote management computer sends to the SP an information request, the SP retrieves the HID collection and transmits the questions and the corresponding options to the remote management computer. In response to a command indicating a selected corresponding option, the SP changes corresponding data of the BIOSSD collection according to the command. When the BIOS executed at the host computer issues a BIOSSD update request to the SP, the SP transmits a copy of the BIOSSD collection to the BIOS chip of the host computer to replace the BIOSSD collection stored in the BIOS chip.

Abstract: A power circuit section generates a first logic power supply voltage and an analog power supply voltage to supply to a first power supply line and a second power supply line, respectively. A regulator steps the first logic power supply voltage down to generate a second logic power supply voltage and supplies the second logic power supply voltage to a third power supply line. A logic circuit controls A source line driving section and A gate line driving section in response to a decrease of a voltage of the first power supply line so that the charge stored in the display panel is discharged. A charge transporting path is configured to transport the charge from the second power supply line to a third power supply line in response to the decrease of the voltage of the first power supply line.

Abstract: Methods and systems may provide for determining whether a runtime disablement condition is met with respect to a sleep state and disabling the sleep state if the runtime disablement condition is met. Additionally, the sleep state may be enabled if a runtime reinstatement condition is met. In one example, determining whether the runtime disablement condition is met includes determining a false entry rate for the sleep state, and comparing the false entry rate to an energy-based threshold, wherein the sleep state is disabled if the false entry rate exceeds the energy-based threshold.

Abstract: A power supply output configuration system/method providing a digitally controlled uninterruptable power supply (UPS) to protected load devices (PLD) configured as power supply units (PSU) serviced by one or more power supply sources (PSS) is disclosed. The system generally includes a number of power supply sources (PSS) that are monitored by power condition sensing (PCS) circuitry that determines individual power source states within the PSS. This physical state information is used by a digitally controlled switching network (DSN) that reconfigures the electrical connections between the PSS and the individual PLD elements to properly route power from the PSS to the PLD in the event of individual PSS failures. The DSN receives phase/voltage state information from the PSS to ensure that current between the PSS and PLD is transferred in a synchronized manner and that PSS resources are properly protected during the switching transition.

Abstract: A dual input power supply system/method providing uninterruptable power to a protected load device (PLD) is disclosed. The system includes hybrid switch devices (HSD) comprising semiconductor and relay/contactors that minimize the OPERATE/RELEASE times associated with switchover from a primary power source (PPS) to a secondary power source (SPS). An operate/release controller (ORC) monitors the condition of power provided by the PPS and SPS and determines the optimal transfer time to activate the HSD and switch between the PPS and SPS based on the PLD configuration. Use of the HSD in conjunction with the ORC permits a wide variety of series permutated AC/DC primary (PPS) and secondary (SPS) power sources, EMI snubbers (EMS), bridge rectifier diodes (BRD), AC-DC converters (ADC), and DC-DC converters (DDC) to service the PLD, while simultaneously reducing storage capacitors normally required to cover the OPERATE/RELEASE times associated with traditional PPS/SPS switchover/failover delays.

Abstract: An information processing apparatus includes a control unit, a processing unit capable of dynamically changing a circuit configuration thereof, and a storage unit configured to store circuit information indicating a circuit configuration to be read into the processing unit, wherein the processing unit reads first circuit information from the storage unit to function as a storage medium for storing a program, and wherein the control unit reads the program from the processing unit to execute the program.

Abstract: A power supply configuration system/method providing a digitally controlled uninterruptable power supply (UPS) to protected load devices (PLD) configured as power supply units (PSU) serviced by one or more power supply sources (PSS) is disclosed. The system generally includes a number of power supply sources (PSS) that are monitored by power condition sensing (PCS) circuitry that determines individual power source states within the PSS. This physical state information is used by a digitally controlled switching network (DSN) that reconfigures the electrical connections between the PSS and the individual PLD elements to properly route power from the PSS to the PLD in the event of individual PSS failures. The DSN receives phase/voltage state information from the PSS to ensure that current between the PSS and PLD is transferred in a synchronized manner and that PSS resources are properly protected during the switching transition.

Abstract: A system for baseboard management controller (BMC) operation is provided. The system includes a computing system including hardware on which an operating system is operable and sensors disposed to sense various attributes of the hardware and a BMC. The BMC is disposed in signal communication with the computing system and is bootable and operative independent of an execution of the operating system. Upon boot initialization of the BMC, the BMC includes an empty reserved database, issues to the computing system a query for a list of the sensors and builds and populates in the reserved database a sensor attribute repository in accordance with sensor data received from the computing system in response to the query and sensor attribute data associated with the sensor data.

Abstract: The present invention aims to easily maintain a state of less power consumption, by providing a data processing apparatus comprising: a registering unit to register therein data for identifying a packet; a receiving unit to receive a packet transmitted through a network; a determining unit to, in a case where the receiving unit receives the packet while the data processing apparatus is operating in a power saving mode, determine whether or not to return the data processing apparatus from the power saving mode, on the basis of the data registered in the registering unit; an analyzing unit to perform an analysis process to the packet flowing on the network; a displaying unit to display a screen indicating a result of the analysis process by the analyzing unit; and an indicating unit to indicate the data to be registered in the registering unit, through the screen displayed by the displaying unit.

Abstract: An uninterruptable power supply (UPS) system/method providing power line conditioning and power factor correction (PFC) that incorporates centralized battery backup energy storage architecture is disclosed. The system generally comprises an AC-DC power supply with active PFC (power factor correction) function, a battery transfer switch, an isolated battery charger placed between the utility power source and battery strings, battery strings connecting the battery charger and the battery transfer switch, EMI/Lightning circuitry that provides lighting/line surge protection as well noise suppression functions, and a controller monitoring the quality of the utility power source. Uninterruptable power for data centers is achieved in this context via use of the battery strings, battery transfer switch, battery charger, and controller system configuration. Disclosed methods associated with this system generally permit the UPS to operate in a distributed fashion in support of computing systems within data centers.

Abstract: A semiconductor device includes a power-up signal generation unit suitable for receiving a first power supply voltage and a second power supply voltage higher the first power supply voltage and generating a power-up signal when the first and second power supply voltage increase to reach target levels, respectively, a voltage level adjusting unit suitable for generating a third power supply voltage by adjusting a voltage level of the second power supply voltage, a boot-up signal generation unit suitable for generating a boot-up signal in response to the power-up signal, and a circuit operation unit suitable for performing a boot-up operation using the third power supply voltage in response to the boot-up signal.

Abstract: A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.

Abstract: A system for baseboard management controller (BMC) operation is provided. The system includes a computing system including hardware on which an operating system is operable and sensors disposed to sense various attributes of the hardware and a BMC. The BMC is disposed in signal communication with the computing system and is bootable and operative independent of an execution of the operating system. Upon boot initialization of the BMC, the BMC includes an empty reserved database, issues to the computing system a query for a list of the sensors and builds and populates in the reserved database a sensor attribute repository in accordance with sensor data received from the computing system in response to the query and sensor attribute data associated with the sensor data.