Patents by Inventor Akira Katayama

Akira Katayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10861525
    Abstract: A nonvolatile storage device includes a first wiring extending in a first direction, a second wiring extending in a second direction, a memory cell between the first and second wirings, a reading circuit configured to read data from the memory cell during a first and a second reading period, a writing circuit configured to write reference data into the memory cell during a writing period between the first and second reading periods, and a determination circuit configured to compare a first voltage which is based on the data read during the first reading period with a second voltage which is based on the data read during the second reading period, to determine the value of the data read during the first reading period. A current is caused to flow in the memory cell during the first reading period, the writing period, and the second reading period.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: December 8, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akira Katayama
  • Publication number: 20200302986
    Abstract: According to one embodiment, a semiconductor memory device comprising: a first memory layer including a plurality of memory units electrically coupled to one another; a first memory area including a first memory unit for data writing of the memory units; a second memory area including a second memory unit for data reading of the memory units; and a controller configured to write data in the first memory unit, shift the data written in the first memory unit to the second memory unit, and read data written in the second memory unit.
    Type: Application
    Filed: September 9, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Akira KATAYAMA
  • Publication number: 20200273513
    Abstract: According to one embodiment, a semiconductor memory device includes control circuit configured to first node to first voltage being based on resistance of memory cell when first data is stored, write second data after first node is charged to first voltage, charge second node to second voltage being based on resistance of memory cell when second data is stored, and determine, based on first and second voltage, whether or not first data is different from second data. Control circuit includes first element including first end coupled to first node, and second end coupled to third node between first and second node, second element including first and second end coupled to first node, and third element including first end coupled to second node and second end coupled to third node.
    Type: Application
    Filed: September 4, 2019
    Publication date: August 27, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Akira KATAYAMA
  • Publication number: 20200090723
    Abstract: A nonvolatile storage device includes a first wiring extending in a first direction, a second wiring extending in a second direction, a memory cell between the first and second wirings, a reading circuit configured to read data from the memory cell during a first and a second reading period, a writing circuit configured to write reference data into the memory cell during a writing period between the first and second reading periods, and a determination circuit configured to compare a first voltage which is based on the data read during the first reading period with a second voltage which is based on the data read during the second reading period, to determine the value of the data read during the first reading period. A current is caused to flow in the memory cell during the first reading period, the writing period, and the second reading period.
    Type: Application
    Filed: February 26, 2019
    Publication date: March 19, 2020
    Inventor: Akira KATAYAMA
  • Publication number: 20190361251
    Abstract: [Object] To provide a see-through display device, a system, a program, and an information processing method capable of improving safety at the time of use. [Solving Means] According to one embodiment of the present technology, there is provided a see-through display device including an error detection unit and a display control unit. The error detection unit detects an error. The display control unit controls display of a see-through display on the basis of a detection result of the error detection unit.
    Type: Application
    Filed: November 28, 2017
    Publication date: November 28, 2019
    Applicant: Sony Semiconductor Solutions Corporation
    Inventors: Takeshi Iwatsu, Tohru Kadono, Akira Katayama
  • Patent number: 10453512
    Abstract: According to one embodiment, a memory device, includes a memory cell; and a first circuit that performs a first read on the memory cell to generate a first voltage, performs a reference read on the memory cell to generate a second voltage, generates first data based on the first voltage and the second voltage, writes the first data in the memory cell on which the first read has been performed, performs a second read on the memory cell in which the first data has been written to generate a third voltage, and determines data that was stored in the memory cell when the first read was performed, based on the first voltage and the third voltage.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: October 22, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akira Katayama
  • Publication number: 20190295622
    Abstract: According to one embodiment, a memory device, includes a memory cell; and a first circuit that performs a first read on the memory cell to generate a first voltage, performs a reference read on the memory cell to generate a second voltage, generates first data based on the first voltage and the second voltage, writes the first data in the memory cell on which the first read has been performed, performs a second read on the memory cell in which the first data has been written to generate a third voltage, and determines data that was stored in the memory cell when the first read was performed, based on the first voltage and the third voltage.
    Type: Application
    Filed: September 11, 2018
    Publication date: September 26, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Akira KATAYAMA
  • Patent number: 10410706
    Abstract: A memory includes a bit line connected to a memory cell and a read circuit to execute reading of data from the memory cell. The read circuit includes a first circuit having a first input terminal and detecting an output signal from the memory cell, a first transistor to control a current supplied to the memory cell based on a first control signal, and a second transistor. One terminal of the first transistor is connected to the first input terminal, the other terminal of the first transistor is connected to one terminal of the second transistor, the other terminal of the second transistor is connected to the bit line, and the one terminal and the other terminal of the first transistor are charged before data is read from the memory cell.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: September 10, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akira Katayama, Katsuyuki Fujita
  • Patent number: 10410704
    Abstract: According to one embodiment, a memory includes a first MTJ element having a first area along a first plane; and second MTJ elements each having a second area along the first plane. The second area is larger than or equal to twice the first area and smaller than or equal to five times the first area. Each of the second MTJ elements includes a first ferromagnet, a second ferromagnet, and a first nonmagnet. Respective magnetizations of respective first ferromagnets of the second MTJ elements are oriented along a first direction. Respective magnetizations of respective second ferromagnets of the second MTJ elements are oriented along a second direction. One of the second MTJ elements is coupled to another one of the second MTJ elements in series or in parallel.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: September 10, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keiji Hosotani, Tatsuya Kishi, Akira Katayama
  • Patent number: 10360976
    Abstract: A memory device includes a sense amplifier including a first input node and a second input node and configured to output a signal based on a difference between input values at the first input node and the second input node; a first path including a memory cell to be selectively connected to the first input node and provided between the first input node and a ground node; and a second path including a reference cell to be selectively connected to the second input node and provided between the second input node and the ground node.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: July 23, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akira Katayama
  • Patent number: 10159942
    Abstract: The present invention provides a separation membrane and a separation membrane element capable of exhibiting a good water production performance even at a high temperature and also excellent handleability and quality. The separation membrane of the present invention includes a separation membrane main body having a feed-side face and a permeate-side face; and a permeate-side channel member fixed onto the permeate-side face of the separation membrane main body, and the permeate-side channel member includes polypropylene as a main component and satisfies the following requirements (a) to (c): (a) a softening point temperature is 60° C. or higher; (b) a tensile elongation in a standard state is 10% or more; and (c) a yield point stress under a wet condition at 50° C. is 2 MPa or more.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: December 25, 2018
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Yoshie Marutani, Hiroyuki Yamada, Hiroho Hirozawa, Kentaro Takagi, Yoshiki Okamoto, Shunsuke Tabayashi, Hiroshi Umetani, Akira Katayama, Takao Sasaki, Masahiro Kimura
  • Patent number: 10107545
    Abstract: An air conditioning apparatus for a vehicle includes a refrigerant heater 41 that is provided between an internal evaporator 8 and a suction side of an electric compressor 20 to be in parallel with an external evaporator 32, and heats a refrigerant which is suctioned into the electric compressor 20; and an air conditioning control apparatus 50 that determines whether the external evaporator 32 is frosted. While the air conditioning apparatus for a vehicle operates in a heating mode, when the air conditioning control apparatus 50 determines that the external evaporator 32 is frosted, a supply of the refrigerant subject to the heat exchange in an internal condenser 9 to the external evaporator 32 is stopped, and the refrigerant is supplied to the refrigerant heater 41, is heated and then, is suctioned into the electric compressor 20.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: October 23, 2018
    Assignee: MITSUBISHI HEAVY INDUSTRIES AUTOMOTIVE THERMAL SYSTEMS CO., LTD.
    Inventors: Masatoshi Morishita, Toshihisa Kondo, Akira Katayama
  • Publication number: 20180277183
    Abstract: According to one embodiment, a memory includes a first MTJ element having a first area along a first plane; and second MTJ elements each having a second area along the first plane. The second area is larger than or equal to twice the first area and smaller than or equal to five times the first area. Each of the second MTJ elements includes a first ferromagnet, a second ferromagnet, and a first nonmagnet. Respective magnetizations of respective first ferromagnets of the second MTJ elements are oriented along a first direction. Respective magnetizations of respective second ferromagnets of the second MTJ elements are oriented along a second direction. One of the second MTJ elements is coupled to another one of the second MTJ elements in series or in parallel.
    Type: Application
    Filed: September 12, 2017
    Publication date: September 27, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keiji HOSOTANI, Tatsuya KISHI, Akira KATAYAMA
  • Publication number: 20180204615
    Abstract: A memory device includes a sense amplifier including a first input node and a second input node and configured to output a signal based on a difference between input values at the first input node and the second input node; a first path including a memory cell to be selectively connected to the first input node and provided between the first input node and a ground node; and a second path including a reference cell to be selectively connected to the second input node and provided between the second input node and the ground node.
    Type: Application
    Filed: March 14, 2018
    Publication date: July 19, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Akira KATAYAMA
  • Publication number: 20180197592
    Abstract: According to one embodiment, a memory includes a bit line connected to a memory cell; and a read circuit to execute reading of data from the memory cell. The read circuit includes a first circuit having a first input terminal and detecting an output signal from the memory cell; a first transistor to control a current supplied to the memory cell based on a first control signal; and a second transistor. One terminal of the first transistor is connected to the first input terminal, the other terminal of the first transistor is connected to one terminal of the second transistor, the other terminal of the second transistor is connected to the bit line, and the one terminal and the other terminal of the first transistor are charged before data is read from the memory cell.
    Type: Application
    Filed: March 6, 2018
    Publication date: July 12, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Akira KATAYAMA, Katsuyuki FUJITA
  • Patent number: 9953707
    Abstract: According to one embodiment, a memory device includes a sense amplifier including a first input node and a second input node, a first path including a memory cell to be selectively connected to the first input node, and a second path including a reference cell to be selectively connected to the second input node, and is configured to change an input value at the second input node in accordance with the state of the memory cell.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: April 24, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akira Katayama
  • Patent number: 9899082
    Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell including a first variable resistance element; a first buffer coupled to the first memory cell; a second memory cell including a second variable resistance element; and a second buffer coupled to the second memory cell. In data write, first data is stored in the first buffer and is transferred to the first memory cell, and second data is stored in the second buffer and is transferred to the second memory cell, and a start of the transferring the first data and the second data is based on a first data transfer signal.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: February 20, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akira Katayama
  • Patent number: 9884536
    Abstract: A refrigerant cycle (16) for cooling as a prototype is provided with: an internal condenser (8) connected to a discharge circuit of an electric compressor (9) and disposed on a downstream of an internal evaporator (7) of an HVAC unit (2); a first heating circuit (18) connected to a receiver (11) through a switching unit (17) arranged on an inlet side of the external condenser (8); and a second heating circuit (23) connected between an outlet side of the receiver (11) and a suction side of the electric compressor (9) and provided with a second expansion valve (20) and an external evaporator (21). A heat pump cycle (24) for heating is formed by a second heating circuit (23) including the electric compressor (9), the internal condenser (8), the switching unit (17), the first heating circuit (18), the receiver (11), the second expansion valve (20), and the external evaporator (21).
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: February 6, 2018
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Akira Katayama, Nobuya Nakagawa, Toshihisa Kondou, Masatoshi Morishita
  • Patent number: 9824736
    Abstract: According to one embodiment, a memory device includes a memory cell array; a generation circuit generating a reference current; a sense amplifier comparing a cell current flowing through a memory cell with the reference current; a first clamp transistor connected between the sense amplifier and the memory cell; a second clamp transistor connected between the sense amplifier and the generation circuit; a first interconnect layer connected to a gate of the first clamp transistor; a second interconnect layer connected to a gate of the second clamp transistor and arranged adjacent to the first interconnect layer; and a first shield line arranged adjacent to one of the first interconnect layer and the second interconnect layer, a fixed voltage being applied to the first shield line.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: November 21, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akira Katayama
  • Patent number: 9767863
    Abstract: According to one embodiment, a memory device includes: a first storage area configured to store data; a first sense amplifier; a first data latch; a first selector configured to select either connection between the first data latch and the first sense amplifier or connection between the first data latch and another sense amplifier; and a second selector configured to select either connection between the first storage area and the first sense amplifier or connection between another storage area and the first sense amplifier.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: September 19, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akira Katayama