Abstract: According to one embodiment, a semiconductor storage device includes a first semiconductor storage area; a second semiconductor storage area; a reference circuit; a sense amplifier senses data stored in the first semiconductor storage area and the second semiconductor storage area; and a control circuit.

Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell including a first variable resistance element; a first buffer coupled to the first memory cell; a second memory cell including a second variable resistance element; and a second buffer coupled to the second memory cell. In data write, first data is stored in the first buffer and is transferred to the first memory cell, and second data is stored in the second buffer and is transferred to the second memory cell, and a start of the transferring the first data and the second data is based on a first data transfer signal.

Abstract: According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.

Abstract: A vehicle heat pump air-conditioning system is provided, which is capable of securing a temperature linearity characteristic during dehumidifying heating, slowing progression of a frost formation on an exterior evaporator during heating, and stably continuing a heating operation while suppressing variations in a blowout temperature. In a cooling refrigeration cycle (14) becoming a base, an interior condenser (8) disposed in a HVAC unit (2) is connected to an exterior condenser (10) in parallel via switching means (15), an exterior evaporator (17) is connected to first decompression means (12) and an interior evaporator (7) in parallel via second decompression means (16), a heating heat pump cycle (18) is configured, the first decompression means (12) and the second decompression means (16) are on-off valve function attached decompression means (12, 16), and the exterior evaporator (17) and the interior evaporator (7) can be simultaneously used during dehumidifying heating and heating.

Abstract: According to one embodiment, a memory device includes: a first storage area configured to store data; a first sense amplifier; a first data latch; a first selector configured to select either connection between the first data latch and the first sense amplifier or connection between the first data latch and another sense amplifier; and a second selector configured to select either connection between the first storage area and the first sense amplifier or connection between another storage area and the first sense amplifier.

Abstract: A magnetic storage device of one embodiment includes a first and second magnetoresistive effect elements. The first magnetoresistive element includes a first magnetic layer having a first coercivity, a second magnetic layer having a second coercivity higher than the first coercivity, and a third magnetic layer having a third coercivity higher than the second coercivity. Magnetization orientations of the second and third magnetic layers are antiparallel. The second magnetoresistive effect element includes a fourth magnetic layer having a fourth coercivity, a fifth magnetic layer having a fifth coercivity higher than the fourth coercivity, and a sixth magnetic layer having a sixth coercivity higher than the fifth coercivity. Magnetization orientations of the fifth and sixth magnetic layers are parallel.

Abstract: According to one embodiment, a semiconductor storage device includes a first semiconductor storage area; a second semiconductor storage area; a reference circuit; a sense amplifier senses data stored in the first semiconductor storage area and the second semiconductor storage area; and a control circuit.

Abstract: The present invention provides a separation membrane and a separation membrane element capable of exhibiting a good water production performance even at a high temperature and also excellent handleability and quality. The separation membrane of the present invention includes a separation membrane main body having a feed-side face and a permeate-side face; and a permeate-side channel member fixed onto the permeate-side face of the separation membrane main body, and the permeate-side channel member includes polypropylene as a main component and satisfies the following requirements (a) to (c): (a) a softening point temperature is 60° C. or higher; (b) a tensile elongation in a standard state is 10% or more; and (c) a yield point stress under a wet condition at 50° C. is 2 MPa or more.

Abstract: According to one embodiment, a memory device includes a sense amplifier including a first input node and a second input node, a first path including a memory cell to be selectively connected to the first input node, and a second path including a reference cell to be selectively connected to the second input node, and is configured to change an input value at the second input node in accordance with the state of the memory cell.

Abstract: A semiconductor storage device includes a first bit line and a second bit line. A nonvolatile memory element and a first cell transistor are connected in series between the first bit line and the second bit line. A sense transistor has a gate connected to a sense node which is provided between the first bit line and the memory element. A read bit line is connected to a source or a drain of the sense transistor. The read bit line is configured to transmit data of the memory element. A sense amplifier is configured to detect the logic of data transmitted from the read bit line.

Abstract: According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.

Abstract: A magnetic storage device of one embodiment includes a first and second magnetoresistive effect elements. The first magnetoresistive element includes a first magnetic layer having a first coercivity, a second magnetic layer having a second coercivity higher than the first coercivity, and a third magnetic layer having a third coercivity higher than the second coercivity. Magnetization orientations of the second and third magnetic layers are antiparallel. The second magnetoresistive effect element includes a fourth magnetic layer having a fourth coercivity, a fifth magnetic layer having a fifth coercivity higher than the fourth coercivity, and a sixth magnetic layer having a sixth coercivity higher than the fifth coercivity. Magnetization orientations of the fifth and sixth magnetic layers are parallel.

Abstract: A memory includes a cell array including nonvolatile memory cells. A power generator generates a power supply voltage for driving the cell array. A receiver receives a command and an address. A controller controls an active state of the cell array, the power generator, and the receiver. In an activation mode, the cell array, the power generator, and the receiver are turned into the active states. In a first power saving mode, the cell array, the power generator, and the receiver are turned into inactive states. In a second power saving mode, the cell array and the power generator are turned into the active states, and the receiver is turned into the inactive state. In a third power saving mode, at least a part of the power generator is turned into the active state, and the cell array and the receiver are turned into the inactive states.

Abstract: A semiconductor storage device includes a first bit line and a second bit line. A nonvolatile memory element and a first cell transistor are connected in series between the first bit line and the second bit line. A sense transistor has a gate connected to a sense node which is provided between the first bit line and the memory element. A read bit line is connected to a source or a drain of the sense transistor. The read bit line is configured to transmit data of the memory element. A sense amplifier is configured to detect the logic of data transmitted from the read bit line.

Abstract: According to one embodiment, according to one embodiment, a resistance change memory includes a memory cell, a sense amplifier, a control circuit and a storage unit. The memory cell includes a resistance change element. The sense amplifier compares a reference current with a cell current flowing through the memory cell. The control circuit calculates offset information of the reference current. The storage unit is provided for the sense amplifier and stores the offset information. The storage unit corresponds to the sense amplifier one to one.

Abstract: A semiconductor storage device includes a first bit line and a second bit line. A nonvolatile memory element and a first cell transistor are connected in series between the first bit line and the second bit line. A sense transistor has a gate connected to a sense node which is provided between the first bit line and the memory element. A read bit line is connected to a source or a drain of the sense transistor. The read bit line is configured to transmit data of the memory element. A sense amplifier is configured to detect the logic of data transmitted from the read bit line.

Abstract: A refrigerant cycle (16) for cooling as a prototype is provided with: an internal condenser (8) connected to a discharge circuit of an electric compressor (9) and disposed on a downstream of an internal evaporator (7) of an HVAC unit (2); a first heating circuit (18) connected to a receiver (11) through a switching unit (17) arranged on an inlet side of the external condenser (8); and a second heating circuit (23) connected between an outlet side of the receiver (11) and a suction side of the electric compressor (9) and provided with a second expansion valve (20) and an external evaporator (21). A heat pump cycle (24) for heating is formed by a second heating circuit (23) including the electric compressor (9), the internal condenser (8), the switching unit (17), the first heating circuit (18), the receiver (11), the second expansion valve (20), and the external evaporator (21).

Abstract: A refrigerant cycle (16) for cooling as a prototype is provided with: an internal condenser (8) connected to a discharge circuit of an electric compressor (9) and disposed on a downstream of an internal evaporator (7) of an HVAC unit (2); a first heating circuit (18) connected to a receiver (11) through a switching unit (17) arranged on an inlet side of the external condenser (8); and a second heating circuit (23) connected between an outlet side of the receiver (11) and a suction side of the electric compressor (9) and provided with a second expansion valve (20) and an external evaporator (21). A heat pump cycle (24) for heating is formed by a second heating circuit (23) including the electric compressor (9), the internal condenser (8), the switching unit (17), the first heating circuit (18), the receiver (11), the second expansion valve (20), and the external evaporator (21).

Abstract: According to one embodiment, a memory system includes a first memory cell array and a second memory cell array; and a control circuit controls data of the first and second memory cell arrays. The control circuit sets, when receiving an initialization instruction, all of the plurality of bits of the first memory cell array at a first value, and sets all of the plurality of bits of the second memory cell array at a second value which is a complementary value of the first value.

Abstract: According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.