Abstract: According to one embodiment, a resistance change type memory includes first to third bit lines, a word line and a memory cell connected to the first to third bit lines and the word line. The memory cell includes a first transistor and a first memory element between the first and third bit lines, a second transistor and a second memory element between the second and third bit lines. Control terminals of the first and second transistors are connected to the word line. The resistance states of the first and second memory elements change to the first or second resistance state in accordance with a write pulse.

Abstract: A vehicle air-conditioning system includes: an HVAC unit that blows air whose temperature has been adjusted by a refrigerant evaporator and a second refrigerant condenser; a heat pump cycle in which a refrigerant compressor, a refrigerant circuit changeover section, a first refrigerant condenser, a first expansion valve, and the refrigerant evaporator are sequentially connected, in which a second expansion valve and a refrigerant/coolant heat exchanger are connected in parallel with the first expansion valve and the refrigerant evaporator, and in which the second refrigerant condenser is connected in parallel with the first refrigerant condenser; and a coolant cycle in which a coolant circulating pump, a ventilation-exhaust-heat recovery unit, a motor/battery, an electric heater, and the refrigerant/coolant heat exchanger are sequentially connected, and in which the ventilation-exhaust-heat recovery unit, the motor/battery, and the electric heater can be selectively used as a heat source.

Abstract: According to one embodiment, a magnetic memory includes a magnetoresistive element includes a first reference layer, a first nonmagnetic layer, a recording layer, a second nonmagnetic layer, and a second reference layer which are sequentially stacked, the recording layer being connected to a terminal to which a high-level voltage is applied, a magnetization direction of the recording layer being variable, magnetization directions of the first and second reference layers being invariable and antiparallel, a first selection transistor connected between a first bit line and the first reference layer, and constituted of an N-channel MOSFET, a second selection transistor connected between a second bit line and the second reference layer, and constituted of an N-channel MOSFET, and a word line connected to gates of the first and second selection transistors.

Abstract: According to one embodiment, a semiconductor memory device includes a first reference cell being arranged in a first cell array, and a plurality of first fuse cells being arranged in the first cell array. The first reference cell and the plurality of first fuse cells are arranged on the same row or column.

Abstract: An information processing apparatus includes a main switch configured to receive on/off-instructions for power supply from a user, a predicting section configured to predict a time period during which a possibility that the main switch receives an on-instruction is high, a connector section capable of connecting an electronic apparatus including a display screen, a communication establishing section configured to execute processing to establish a state allowing communication with an electronic apparatus connected to the connector section, a black-screen output section capable of outputting a black-screen signal to the electronic apparatus via the connector section, and a startup section configured to start, during a time period predicted by the predicting section and when the main switch is off, the communication establishing section and the black-screen output section, and to cause the black-screen output section to continue to output the black-screen signal until the main switch is turned on.

Abstract: A semiconductor memory device includes a memory cell array disposing a plurality of memory cells at each intersection of word lines and bit lines, the memory cell including one pair of cross-connected inverters including a transistor, a first dummy transistor having a threshold voltage which has a certain relationship with a threshold voltage of the transistor of the memory cell, a dummy bit line connected to one end of the first dummy transistor, and the dummy bit line charged so as to have a predetermined voltage, a dummy transistor control circuit configured to control conduction of the first dummy transistor, and a word line driver configured to supply a word line voltage to the word line connected to the selected memory cell, and the word line driver configured to change a rise time of the word line voltage in accordance with a change in a voltage of the dummy bit line.

Abstract: A fluid separation element is provided including: a membrane winding having two ends and obtained by layering a separation membrane, a feed water channel material, and a permeate channel material and spirally winding them; and one or more anti-telescoping devices attached to one or both of the ends of the membrane winding, wherein a brine seal fitting groove is provided in an outer circumferential surface of the anti-telescoping device and a hole that communicates with a feed water channel side is provided inside the groove. When the anti-telescoping devices are attached to the both ends of the membrane winding, a brine seal is fitted into the groove of the upstream-side anti-telescoping device and no brine seal is fitted into the groove of the downstream-side anti-telescoping device.

Abstract: According to one embodiment, a semiconductor storage device includes a memory cell array, word lines, a driver, and a word-line-potential control circuit. In the memory cell array, memory cells are arranged in a matrix shape in a row direction and a column direction. The word lines perform row selection for the memory cell array during readout of data. The driver drives the word lines. The word-line-potential control circuit controls potential of the word lines such that, during the readout of data, gradient of rising of potential of the word lines to first potential is larger than gradient of further rising of the potential from the first potential to second potential.

Abstract: A semiconductor memory device includes a memory cell array disposing a plurality of memory cells at each intersection of word lines and bit lines, the memory cell including one pair of cross-connected inverters including a transistor, a first dummy transistor having a threshold voltage which has a certain relationship with a threshold voltage of the transistor of the memory cell, a dummy bit line connected to one end of the first dummy transistor, and the dummy bit line charged so as to have a predetermined voltage, a dummy transistor control circuit configured to control conduction of the first dummy transistor, and a word line driver configured to supply a word line voltage to the word line connected to the selected memory cell, and the word line driver configured to change a rise time of the word line voltage in accordance with a change in a voltage of the dummy bit line.

Abstract: A semiconductor memory device includes a memory cell which includes first and second inverter circuits. Each of the first and second inverter circuits includes a load transistor which includes a source connected to a first power supply terminal, and a driving transistor which includes a drain connected to a drain of the load transistor via a memory node, a gate connected to a gate of the load transistor, a source connected to a second power supply terminal, and a back gate connected to a third power supply terminal. A first power supply voltage is applied to the first power supply terminal. A ground voltage is applied to the second power supply terminal. A source voltage higher than the ground voltage is applied to the third power supply terminal.

Abstract: A semiconductor memory device includes a first inverter circuit and a second inverter circuit, a first transfer gate which is connected between a first power node of the first inverter circuit and a first bit line, a second transfer gate which is connected between a second power node of the second inverter circuit and a second bit line, a first word line connected to gate terminals of the first transfer gate and the second transfer gate, a first read transistor connected between the first power node and a second word line, a second read transistor connected between the second power node and the second word line, and an application circuit which is connected to the second word line, and applies a read voltage to the second word line in reading data.

Abstract: A semiconductor memory device includes a memory cell which includes first and second inverter circuits. Each of the first and second inverter circuits includes a load transistor which includes a source connected to a first power supply terminal, and a driving transistor which includes a drain connected to a drain of the load transistor via a memory node, a gate connected to a gate of the load transistor, a source connected to a second power supply terminal, and a back gate connected to a third power supply terminal. A first power supply voltage is applied to the first power supply terminal. A ground voltage is applied to the second power supply terminal. A source voltage higher than the ground voltage is applied to the third power supply terminal.

Abstract: A semiconductor memory device includes a first inverter circuit and a second inverter circuit, a first transfer gate which is connected between a first power node of the first inverter circuit and a first bit line, a second transfer gate which is connected between a second power node of the second inverter circuit and a second bit line, a first word line connected to gate terminals of the first transfer gate and the second transfer gate, a first read transistor connected between the first power node and a second word line, a second read transistor connected between the second power node and the second word line, and an application circuit which is connected to the second word line, and applies a read voltage to the second word line in reading data.

Abstract: To meet a demand for changing a print medium size, particularly for increasing the size of print medium while at the same time satisfying the demand for higher printing speed. To that end, a plurality of printer units (116), which are spatially independent of each other (separate from each other) and also independent in the signal system and the ink system, are arranged in an appropriate layout to allow for a line-sequential printing. An information processing device (100) divides a generated image into a plurality of pieces of print data and transfers them to the plurality of printer units. A transport device (117) is installed to feed a large-sized print medium to an area where the plurality of printer units are arranged. The transport device transfers to each of the plurality of printer units a print timing signal corresponding to the position of each printer unit.

Abstract: The main controller of an ink-jet printer sets a read address in a driver controller to read out image data from an image memory which stores image data to be printed, in units of print lines. The driver controller reads out image data of one line from the image memory in accordance with the set address to print the image of one line, and conveys printing paper in synchronism with this printing. The main controller controls setting of the read address in the driver controller to execute magnification processing in the direction of conveyance on the basis of a set correction amount. When appropriate magnification processing is performed for print image data, any mechanical error of the conveyor mechanism is absorbed.

Abstract: An output apparatus which produces the print output by saving in a first memory print data input via a two-way interface, and converting the print data into the print out information, comprising a second memory different from the first memory for saving the print data with a print ID number added which is input via the interface, a retrieving unit for retrieving corresponding print data of the second memory based on a print ID number input from the outside, and an output unit for outputting the retrieved print data converted into the print out information.

Abstract: A novel benzimidazole derivative or a salt thereof is provided, which is represented by the formula: wherein R1 represents an alkyl group, etc., R2 represents a substituted or unsubstituted aromatic lower alkyl group, R3 represents an alkyl group, etc., and -X- is represented by the following formula (V): etc. This derivative or a salt thereof is useful as medicine.

Abstract: The main controller of an ink-jet printer sets a read address in a driver controller to read out image data from an image memory which stores image data to be printed, in units of print lines. The driver controller reads out image data of one line from the image memory in accordance with the set address to print the image of one line, and conveys printing paper in synchronism with this printing. The main controller controls setting of the read address in the driver controller to execute magnification processing in the direction of conveyance on the basis of a set correction amount. When appropriate magnification processing is performed for print image data, any mechanical error of the conveyor mechanism is absorbed.

Abstract: A camera includes a shutter unit for limiting the exposure time to a record medium, a shutter time setting unit for setting the shutter time of the shutter unit, a shutter drive and control unit for driving and controlling the shutter unit, a shutter condition detecting unit for detecting the condition of the shutter unit, a manifesting unit for manifesting the result detected by the shutter condition detecting unit, a manifestation control unit for driving and controlling the manifesting unit and a memory unit for previously storing inherent data to detect with the shutter condition detecting unit whereby a photographer is informed of the fact that the detection accuracy of the detecting element is insufficient for a shutter time, thus dealing with the situation. The manifestation control unit drives the shutter condition detecting unit, based on a shutter time set by the shutter time setting unit and inherent data stored in the memory unit, thus notifying the shutter condition detecting unit of the result.

Abstract: A printing method and apparatus in which basic image data and information of the printing position of the image data on a recording medium are input from a data source and stored in advance, and the designated image data is bitmapped at the printing position to print an image, thereby increasing the printing speed, and a printing system including the printing apparatus. In this system, image data sent from a host is registered as a basic image, and the image is bitmapped in an image memory on the basis of the information of the printing position, of the stored basic image data on a printing paper sheet, sent from the host. The image data bitmapped in the image memory is then output to a printhead to print the image.