Abstract: A vehicle air-conditioning system includes an HVAC unit that blows air whose temperature is adjusted by a refrigerant evaporator and a second refrigerant condenser. The system includes a heat pump cycle in which a refrigerant compressor, a refrigerant circuit changeover section, a first refrigerant condenser, a first expansion valve, and the refrigerant evaporator are sequentially connected. The system includes a second expansion valve and a refrigerant heat exchanger connected in parallel with the first expansion valve and the refrigerant evaporator. The second refrigerant condenser is connected in parallel with the first refrigerant condenser. The system includes a coolant cycle in which a coolant circulating pump, a ventilation-exhaust-heat recovery unit, a motor/battery, an electric heater, and the refrigerant heat exchanger are sequentially connected, and the ventilation-exhaust-heat recovery unit, motor/battery, and electric heater can be selectively used as a heat source.

Abstract: According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.

Abstract: According to one embodiment, a resistance change memory includes the following structure. A memory cell includes a resistance change element and a transistor. A sense amplifier reads data stored in the memory cell. A control circuit controls the reading by the sense amplifier, and outputs a first signal to control the start of precharging of the bit line, a second signal to control a cell current running through the memory cell, and a third signal to control the start of the activation of the sense amplifier. A second word line has an interconnect structure similar to that of the first word line. A monitor circuit detects a first signal delay in the second word line, and outputs the first signal to the sense amplifier in accordance with the first signal delay.

Abstract: A semiconductor storage device includes a first bit line and a second bit line. A nonvolatile memory element and a first cell transistor are connected in series between the first bit line and the second bit line. A sense transistor has a gate connected to a sense node which is provided between the first bit line and the memory element. A read bit line is connected to a source or a drain of the sense transistor. The read bit line is configured to transmit data of the memory element. A sense amplifier is configured to detect the logic of data transmitted from the read bit line.

Abstract: A vehicle heat pump air-conditioning system is provided, which is capable of securing a temperature linearity characteristic during dehumidifying heating, slowing progression of a frost formation on an exterior evaporator during heating, and stably continuing a heating operation while suppressing variations in a blowout temperature. In a cooling refrigeration cycle (14) becoming a base, an interior condenser (8) disposed in a HVAC unit (2) is connected to an exterior condenser (10) in parallel via switching means (15), an exterior evaporator (17) is connected to first decompression means (12) and an interior evaporator (7) in parallel via second decompression means (16), a heating heat pump cycle (18) is configured, the first decompression means (12) and the second decompression means (16) are on-off valve function attached decompression means (12, 16), and the exterior evaporator (17) and the interior evaporator (7) can be simultaneously used during dehumidifying heating and heating.

Abstract: A semiconductor device includes a first latch unit that latches write data based on a strobe signal, a second latch unit that receives the write data latched in the first latch unit based on a first clock signal, and a strobe generation unit that generates the strobe signal and supplies it to the first latch unit. The strobe generation unit includes a bit shift counter, which receives a second clock signal and outputs a bit shift signal having a logic level that is inverted every plural clock cycles of the second clock signal, and a logic gate that outputs the second clock signal as the strobe signal according to the bit shift signal. The latch period of the write data in the first latch part is determined by the period of the strobe signal and also the period of the bit shift signal.

Abstract: According to one embodiment, a memory includes a resistance change element connected between first and second conductive lines, a write buffer which writes data in the resistance change element by flowing a write current to the resistance change element through the first and second conductive lines in a writing, a current/voltage converter which converts the write current into a sense voltage, the converter provided in the write buffer, the write buffer being non-activated when the sense voltage is larger than a first threshold value.

Abstract: An air conditioning apparatus for a vehicle includes a refrigerant heater 41 that is provided between an internal evaporator 8 and a suction side of an electric compressor 20 to be in parallel with an external evaporator 32, and heats a refrigerant which is suctioned into the electric compressor 20; and an air conditioning control apparatus 50 that determines whether the external evaporator 32 is frosted. While the air conditioning apparatus for a vehicle operates in a heating mode, when the air conditioning control apparatus 50 determines that the external evaporator 32 is frosted, a supply of the refrigerant subject to the heat exchange in an internal condenser 9 to the external evaporator 32 is stopped, and the refrigerant is supplied to the refrigerant heater 41, is heated and then, is suctioned into the electric compressor 20.

Abstract: According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.

Abstract: According to one embodiment, a memory includes a resistance change element connected between first and second conductive lines, a write buffer which writes data in the resistance change element by flowing a write current to the resistance change element through the first and second conductive lines in a writing, a current/voltage converter which converts the write current into a sense voltage, the converter provided in the write buffer, the write buffer being non-activated when the sense voltage is larger than a first threshold value.

Abstract: According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.

Abstract: A memory includes a cell array including nonvolatile memory cells. A power generator generates a power supply voltage for driving the cell array. A receiver receives a command and an address. A controller controls an active state of the cell array, the power generator, and the receiver. In an activation mode, the cell array, the power generator, and the receiver are turned into the active states. In a first power saving mode, the cell array, the power generator, and the receiver are turned into inactive states. In a second power saving mode, the cell array and the power generator are turned into the active states, and the receiver is turned into the inactive state. In a third power saving mode, at least a part of the power generator is turned into the active state, and the cell array and the receiver are turned into the inactive states.

Abstract: The control circuit selects, as the first reference cell, the first memory cell having a maximum reading current supplied by turning on the first select transistor in a state in which resistance values of the first memory cells are all increased. The control circuit selects, as the second reference cell, the second memory cell having a maximum reading current supplied by turning on the second select transistor in a state in which resistance values of the second memory cells are all increased. The first reference-current setting circuit sets, as the first reference current, a current obtained by adding a first adjusting current to the reading current of the first reference cell. The second reference-current setting circuit sets, as the second reference current, a current obtained by adding a second adjusting current to the reading current of the second reference cell.

Abstract: According to one embodiment, a magnetic memory includes a magnetoresistive element includes a first reference layer, a first nonmagnetic layer, a recording layer, a second nonmagnetic layer, and a second reference layer which are sequentially stacked, the recording layer being connected to a terminal to which a high-level voltage is applied, a magnetization direction of the recording layer being variable, magnetization directions of the first and second reference layers being invariable and antiparallel, a first selection transistor connected between a first bit line and the first reference layer, and constituted of an N-channel MOSFET, a second selection transistor connected between a second bit line and the second reference layer, and constituted of an N-channel MOSFET, and a word line connected to gates of the first and second selection transistors.

Abstract: A semiconductor device includes a first latch unit that latches write data based on a strobe signal, a second latch unit that receives the write data latched in the first latch unit based on a first clock signal, and a strobe generation unit that generates the strobe signal and supplies it to the first latch unit. The strobe generation unit includes a bit shift counter, which receives a second clock signal and outputs a bit shift signal having a logic level that is inverted every plural clock cycles of the second clock signal, and a logic gate that outputs the second clock signal as the strobe signal according to the bit shift signal. The latch period of the write data in the first latch part is determined by the period of the strobe signal and also the period of the bit shift signal.

Abstract: An information processing apparatus includes a main switch configured to receive on/off-instructions for power supply from a user, a predicting section configured to predict a time period during which a possibility that the main switch receives an on-instruction is high, a connector section capable of connecting an electronic apparatus including a display screen, a communication establishing section configured to execute processing to establish a state allowing communication with an electronic apparatus connected to the connector section, a black-screen output section capable of outputting a black-screen signal to the electronic apparatus via the connector section, and a startup section configured to start, during a time period predicted by the predicting section and when the main switch is off, the communication establishing section and the black-screen output section, and to cause the black-screen output section to continue to output the black-screen signal until the main switch is turned on.

Abstract: A refrigerant cycle (16) for cooling as a prototype is provided with: an internal condenser (8) connected to a discharge circuit of an electric compressor (9) and disposed on a downstream of an internal evaporator (7) of an HVAC unit (2); a first heating circuit (18) connected to a receiver (11) through a switching unit (17) arranged on an inlet side of the external condenser (8); and a second heating circuit (23) connected between an outlet side of the receiver (11) and a suction side of the electric compressor (9) and provided with a second expansion valve (20) and an external evaporator (21). A heat pump cycle (24) for heating is formed by a second heating circuit (23) including the electric compressor (9), the internal condenser (8), the switching unit (17), the first heating circuit (18), the receiver (11), the second expansion valve (20), and the external evaporator (21).

Abstract: A fluid separation element is provided including: a membrane winding having two ends and obtained by layering a separation membrane, a feed water channel material, and a permeate channel material and spirally winding them; and one or more anti-telescoping devices attached to one or both of the ends of the membrane winding, wherein a brine seal fitting groove is provided in an outer circumferential surface of the anti-telescoping device and a hole that communicates with a feed water channel side is provided inside the groove. When the anti-telescoping devices are attached to the both ends of the membrane winding, a brine seal is fitted into the groove of the upstream-side anti-telescoping device and no brine seal is fitted into the groove of the downstream-side anti-telescoping device.

Abstract: The control circuit selects, as the first reference cell, the first memory cell having a maximum reading current supplied by turning on the first select transistor in a state in which resistance values of the first memory cells are all increased. The control circuit selects, as the second reference cell, the second memory cell having a maximum reading current supplied by turning on the second select transistor in a state in which resistance values of the second memory cells are all increased. The first reference-current setting circuit sets, as the first reference current, a current obtained by adding a first adjusting current to the reading current of the first reference cell. The second reference-current setting circuit sets, as the second reference current, a current obtained by adding a second adjusting current to the reading current of the second reference cell.