Patents by Inventor Chien-Hung Liu
Chien-Hung Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984419Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.Type: GrantFiled: July 26, 2022Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Hung Chen, Yu-Nu Hsu, Chun-Chen Liu, Heng-Chi Huang, Chien-Chen Li, Shih-Yen Chen, Cheng-Nan Hsieh, Kuo-Chio Liu, Chen-Shien Chen, Chin-Yu Ku, Te-Hsun Pang, Yuan-Feng Wu, Sen-Chi Chiang
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Patent number: 11984516Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.Type: GrantFiled: February 16, 2023Date of Patent: May 14, 2024Assignee: TONG HSING ELECTRONIC INDUSTRIES, LTD.Inventors: Fu-Chou Liu, Jui-Hung Hsu, Yu-Chiang Peng, Chien-Chen Lee, Ya-Han Chang, Li-Chun Hung
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Patent number: 11978740Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.Type: GrantFiled: February 17, 2022Date of Patent: May 7, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Harry-Hak-Lay Chuang, Kuo-Ching Huang, Wei-Cheng Wu, Hsin Fu Lin, Henry Wang, Chien Hung Liu, Tsung-Hao Yeh, Hsien Jung Chen
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Publication number: 20240136346Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.Type: ApplicationFiled: April 17, 2023Publication date: April 25, 2024Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
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Patent number: 11967652Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.Type: GrantFiled: February 16, 2023Date of Patent: April 23, 2024Assignee: TONG HSING ELECTRONIC INDUSTRIES, LTD.Inventors: Fu-Chou Liu, Jui-Hung Hsu, Yu-Chiang Peng, Chien-Chen Lee, Ya-Han Chang, Li-Chun Hung
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Publication number: 20240112842Abstract: An inductor and a method of forming the same are provided. The inductor includes a patterned wire structure. The patterned wire structure includes a conductive core, a dielectric film and a magnetic shell. The conductive core includes a pair of end surfaces and an outer surface between the pair of end surfaces. The dielectric film covers the outer surface. The magnetic shell covers the dielectric film. The dielectric film is between the conductive core and the magnetic shell.Type: ApplicationFiled: January 10, 2023Publication date: April 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Sheng Lu, Chien-Hung Liu, Nuo Xu
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Patent number: 11949226Abstract: An external power supply system for spindles is revealed. The external power supply system includes a tool holder, a rectifier circuit, an overvoltage protection circuit. and a buck/boost converter. The tool holder receives an external power source of a spindle while the rectifier circuit converts the external power source into a rectified output signal with a power factor through step-down transformation. The overvoltage protection circuit is used to check whether the rectified output signal is larger than an overvoltage signal for outputting an operating potential or a non-operating potential. The buck/boost converter is used for receiving the rectified output signal with the power factor and converting the rectified output signal to an output voltage according to the power factor. Then the output voltage is provided to a load of a low voltage power supply, a high voltage power supply, or a constant voltage power supply.Type: GrantFiled: July 19, 2021Date of Patent: April 2, 2024Assignee: NATIONAL CHUNG HSING UNIVERSITYInventors: Chien-Hung Liu, Yu-Hung Li
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Publication number: 20240105644Abstract: A semiconductor die package includes a high dielectric constant (high-k) dielectric layer over a device region of a first semiconductor die that is bonded with a second semiconductor die in a wafer on wafer (WoW) configuration. A through silicon via (TSV) structure may be formed through the device region. The high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. In particular, the electron carriers in high-k dielectric layer attracts hole charge carriers in device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the TSV structure. Accordingly, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die.Type: ApplicationFiled: January 6, 2023Publication date: March 28, 2024Inventors: Tsung-Hao YEH, Chien Hung LIU, Hsien Jung CHEN, Hsin Heng WANG, Kuo-Ching HUANG
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Publication number: 20240104746Abstract: The present invention discloses a vessel tracking and monitoring system and operating method thereof. Specifically, the vessel tracking and monitoring system comprises at least one camera, a processing module and a storage module. On the other hand, the processing module may keep the water object which is detected and recognized by the at least one camera in the center area of a monitoring screen. Therefore, the present invention may track and recognize the type of the at least one water object, assisting areas such as ports in managing and tracking water object arrivals and departures under various environmental conditions.Type: ApplicationFiled: December 15, 2022Publication date: March 28, 2024Inventors: CHIA-YU WU, YAN-SHENG SONG, YU-TING PENG, CHIEN-HUNG LIU
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Publication number: 20240096941Abstract: A semiconductor structure includes a substrate with a first surface and a second surface opposite to the first surface, a first and a second shallow trench isolations disposed in the substrate and on the second surface, a deep trench isolation structure in the substrate and coupled to the first shallow trench isolation, a first dielectric layer disposed on the first surface and coupled to the deep trench isolation structure, a second dielectric layer disposed over the first dielectric layer and coupled to the deep trench isolation structure, a third dielectric layer comprising a horizontal portion disposed over the second dielectric layer and a vertical portion coupled to the horizontal portion, and a through substrate via structure penetrating the substrate from the first surface to the second surface and penetrating the second shallow trench isolation.Type: ApplicationFiled: January 11, 2023Publication date: March 21, 2024Inventors: SHIH-JUNG TU, PO-WEI LIU, TSUNG-YU YANG, YUN-CHI WU, CHIEN HUNG LIU
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Publication number: 20240088026Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.Type: ApplicationFiled: January 17, 2023Publication date: March 14, 2024Inventors: Yi Ching Ong, Wei-Cheng Wu, Chien Hung Liu, Harry-Haklay Chuang, Yu-Sheng Chen, Yu-Jen Wang, Kuo-Ching Huang
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Publication number: 20240047508Abstract: A semiconductor structure includes an inductive metal line located in a dielectric material layer that overlies a semiconductor substrate and laterally encloses a first area; and an array of first ferromagnetic plates including a first ferromagnetic material and overlying or underlying the inductive metal line. For any first point that is selected within volumes of the first ferromagnetic plates, a respective second point exists within a horizontal surface of the inductive metal line such that a line connecting the first point and the second point is vertical or has a respective first taper angle that is less than 20 degrees with respective to a vertical direction. The magnetic field passing through the first ferromagnetic plates is applied generally along a hard direction of magnetization and the hysteresis effect is minimized.Type: ApplicationFiled: August 8, 2022Publication date: February 8, 2024Inventors: Yu-Sheng Chen, Hsien Jung Chen, Kuen-Yi Chen, Chien Hung Liu, Yi Ching Ong, Yu-Jen Wang, Kuo-Ching Huang, Harry-Hak-Lay Chuang
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Patent number: 11894425Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.Type: GrantFiled: February 6, 2023Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yun-Chi Wu, Tsung-Yu Yang, Cheng-Bo Shu, Chien Hung Liu
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Patent number: 11854625Abstract: A device is disclosed herein. The device includes at least two transmit portions and at least one contact portion. Each of the at least two transmit portions is configured to receive a bit line signal. The at least one contact portion is couple to the at least two transmit portions respectively and configured to transmit the bit line signals from the least two transmit portions to a source line.Type: GrantFiled: March 4, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Pin Chang, Chien-Hung Liu, Chih-Wei Hung
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Patent number: 11837643Abstract: A semiconductor device includes a substrate, a gate structure disposed over the substrate, a drain structure disposed in the substrate, and a source structure disposed in the substrate on an n opposite side of the gate structure from the drain structure. The substrate includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and an insulating layer sandwiched between the first semiconductor layer and the second semiconductor layer. The source structure and the drain structure include a same conductivity type. The source structure includes at least an epitaxial layer. The source structure extends deeper into the substrate than the drain structure.Type: GrantFiled: March 14, 2021Date of Patent: December 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventor: Chien Hung Liu
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Publication number: 20230387020Abstract: The present disclosure relates to an integrated chip including a first dielectric layer overlying a substrate and a first conductive interconnect within the first dielectric layer. A bonding layer is over the first dielectric layer. The bonding layer includes a bonding dielectric layer and a bonding interconnect in the bonding dielectric layer. A first charged dielectric layer is along a bottom of the first dielectric layer. A second charged dielectric layer is along a top of the first dielectric layer. The first charged dielectric layer and the second charged dielectric layer have a same polarity.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Inventors: Chien Hung Liu, Kuo-Ching Huang, Harry-Hak-Lay Chuang, Wei-Cheng Wu
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Publication number: 20230387131Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a substrate. The substrate includes a metal layer, a device layer disposed over the metal layer, and an insulating layer disposed vertically between the metal layer and the device layer. A semiconductor device is disposed on the device layer. An interlayer dielectric (ILD) layer is disposed over the semiconductor device and the substrate.Type: ApplicationFiled: August 8, 2023Publication date: November 30, 2023Inventors: Harry-Hak-Lay Chuang, Hsin Fu Lin, Chien Hung Liu
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Patent number: 11801825Abstract: An unmanned ground vehicle (UGV) includes one or more motors configured to drive one or more wheels of the UGV, a memory storing instructions, and a processor coupled to the one or more motors and the memory. The processor is configured to execute the instructions to cause the UGV to determine location information of a movable target; calculate a direction and a speed for the unmanned ground vehicle based on the determined location information; and drive the one or more motors to move the unmanned ground vehicle in the calculated direction at the calculated speed to follow the movable target when the movable target moves.Type: GrantFiled: March 3, 2022Date of Patent: October 31, 2023Assignee: GEOSAT Aerospace & TechnologyInventors: Hsin-Yuan Chen, Chien-Hung Liu, Wei-Hao Wang, Yi-Bin Lin, Yi-Chiang Yang
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Publication number: 20230261004Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device on the top semiconductor layer.Type: ApplicationFiled: February 17, 2022Publication date: August 17, 2023Inventors: Harry-Hak-Lay CHUANG, Kuo-Ching HUANG, Wei-Cheng WU, Hsin Fu LIN, Henry WANG, Chien Hung LIU, Tsung-Hao YEH, Hsien Jung CHEN
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Publication number: 20230209836Abstract: A memory device having a 3D structure provides MFMIS-FET memory cells with a high chip area density. The memory device includes a stack of memory cell layers interleaved with insulating layers. Channel vias penetrate through the stack. Channels of the memory cells are disposed in the channel vias. MFM portions of memory cells are sandwiched between the insulating layers in areas lateral to the channel vias. The MFM portions may be radially distributed from the channel vias and include a floating gate, a ferroelectric layer, and a gate electrode. The gate electrodes associated with a plurality of MFM structures may be united into a word line gate. The ferroelectric layer may wrap around the word line gate, whereby the ferroelectric layer is disposed above and below the word line gate as well as between the word line gate and each of the floating gates.Type: ApplicationFiled: April 20, 2022Publication date: June 29, 2023Inventors: Kuo-Pin Chang, Chien Hung Liu