Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

Abstract: A tracking-distance-measuring system capable of tracking a torso object is provided. The tracking-distance-measuring system includes: an image sensor, a controller, a distance-measuring device, and an actuator device. The image sensor is configured to capture an input image. The controller is configured to analyze the input image to recognize a torso object from the input image, and calculate an offset distance between a center of the torso object and a central axis of the input image. The actuator device is configured to carry the distance-measuring device. The controller controls the actuator device to calibrate an offset angle between the distance-measuring device and the recognized torso object according to the offset distance. In response to calibrating the offset angle, the distance-measuring device emits energy and receives reflected energy to detect an object distance of the torso object.

Abstract: A keyboard device includes a membrane circuit board, a key frame, a position-limiting frame and a key structure. The key frame is located over the membrane circuit board. The position-limiting frame is located over the key frame. The key frame includes a first frame body and a first receiving hole. The first receiving hole runs through the first frame body along a vertical direction. The position-limiting frame includes a second frame body and a second receiving hole. The second receiving hole runs through the second frame body along the vertical direction. The second receiving hole is in communication with the first receiving hole. The key structure includes a keycap and a protrusion part. The keycap is movable within the first receiving hole and the second receiving hole. A portion of the protrusion part is located under the second frame body.

Abstract: A tracking and ranging system includes a thermal sensor device, a controller, a ranging device and a transmission device. The thermal sensor device is configured to capture a thermal image. The controller analyzes the thermal image to identify the main heat source from among the heat sources displayed in the thermal image, and obtain an offset distance between the center points of the main heat source and the thermal image. The ranging device is coupled to the controller. The transmission device loads the ranging device and is coupled to the controller. The controller controls the motion of the transmission device in accordance with the offset distance to correct the offset angle between the ranging device and the object corresponding to the main heat source. After correcting the offset angle, the ranging device detects a first distance to the object by transmitting energy and receiving reflected energy.

Abstract: An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high ? dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

Abstract: Embodiments of the present invention provide a method of processing a surface of a polysilicon and a method of processing a surface of a substrate assembly. The method of processing a surface of a polysilicon includes forming a material film on the surface of the polysilicon; and processing, by using a chemico-mechanical polishing technology, the surface of the polysilicon on which the material film is formed. The material film is selected such that the polysilicon is preferentially removed in a polishing process.

Abstract: An ultrasound ranging device is provided. The ultrasound ranging device includes an ultrasound transmitter, an ultrasound receiver, a light sensor and a processor. The ultrasound transmitter transmits an ultrasonic signal. The ultrasound receiver receives a reflected signal which is generated when the ultrasonic signal meets an obstacle. The light sensor receives light-source data from an external light-source device. The processor is coupled to the light sensor to obtain the light-source data from the light sensor. The processor performs a time calibration according to the light-source data. In addition, after the time calibration, according to barcode information corresponding to the processor, the processor determines the time interval in which the ultrasound transmitter transmits the ultrasonic signal.

Abstract: An ultrasound ranging device is provided. The ultrasound ranging device includes an ultrasound transmitter, an ultrasound receiver, a random number generator and a processor. The ultrasound transmitter transmits an ultrasonic signal. The ultrasound receiver receives a reflected signal which is generated when the ultrasonic signal meets an obstacle. The random number generator generates a random number. The processor is coupled to the random number generator to obtain the random number and according to the random number, the processor determines the delay time for the ultrasound transmitter transmitting the ultrasonic signal. After the delay time, the ultrasound transmitter transmits the ultrasonic signal to perform ultrasound ranging.

Abstract: A keyboard device and a manufacturing method of the keyboard device are provided. The keyboard device includes a base plate, a membrane circuit board and a key. A connecting structure with an upper connecting part is protruded from the base plate. The membrane circuit board includes a first film layer with an extension part. A clearance space is formed between the extension part and the base plate. An end part of the stabilizer bar of the keycap is clamped between the upper connecting part and the extension part. While the stabilizer bar is moved, the end part of the stabilizer bar is slid between the upper connecting part and the extension part. Moreover, the end part of the stabilizer bar and the extension part are interfered with each other and sunken downwardly into the clearance space.

Abstract: A thin-film transistor (TFT) and a manufacturing method thereof, an array substrate and a display device are provided. The TFT includes: a base substrate; a gate electrode and a gate insulating layer, disposed on the base substrate; and an active layer, wherein the gate insulating layer is disposed between the active layer and the gate electrode; the active layer includes a channel region and a doped region disposed on at least one side of the channel region; and the gate insulating layer is provided with a protrusion which is disposed between the doped region and the gate electrode.

Abstract: An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high ? dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate.

Abstract: A luminous keyboard includes at least one key, a switch circuit board, a supporting plate, a backlight module, a reflecting plate and a light-sheltering plate. The backlight module emits a light beam. The backlight module is arranged between the reflecting plate and the light-sheltering plate. A periphery region of the reflecting plate and a periphery region of the light-sheltering plate are thermally laminated or laser welded to define a sealed structure. Since the periphery region of the backlight module is sealed by the sealed structure, the light beam is not leaked out through the periphery region of the backlight module. The space occupied by the sealed structure is not very large. Consequently, the volume of the luminous keyboard is reduced.

Abstract: A semiconductor device includes a substrate, a gate structure disposed over the substrate, a drain structure disposed in the substrate, and a source structure disposed in the substrate on an n opposite side of the gate structure from the drain structure. The substrate includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and an insulating layer sandwiched between the first semiconductor layer and the second semiconductor layer. The source structure and the drain structure include a same conductivity type. The source structure includes at least an epitaxial layer. The source structure extends deeper into the substrate than the drain structure.

Abstract: A memory device includes: a conductive layer coupled to a reference voltage level; a first storage portion vertically coupled to a first surface of the conductive layer; and a second storage portion vertically coupled to a second surface of the conductive layer; wherein the second surface is opposite to the first surface.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

Abstract: A chip package includes a chip, a dam layer, a permanent adhesive layer, a support, a buffer layer, a redistribution layer, a passivation layer, and a conducting structure. A conducting pad and a sensing device of the chip are located on a first surface of a substrate of the chip, and the conducting pad protrudes from the side surface of the substrate. The dam layer surrounds the sensing device. The permanent adhesive layer is between the support and the substrate. The support and the permanent adhesive layer have a trench to expose the conducting pad. The buffer layer is located on the support. The redistribution layer is located on the buffer layer and on the support, the permanent adhesive layer, and the conducting pad facing the trench. The passivation layer covers the redistribution layer, the buffer layer, and the conducting pad.

Abstract: A chip package including a first substrate is provided. The first substrate includes a sensing device. A second substrate is attached onto the first substrate and includes an integrated circuit device. A first conductive structure is electrically connected to the sensing device and the integrated circuit device through a redistribution layer disposed on the first substrate. An insulating layer covers the first substrate, the second substrate and the redistribution layer. The insulating layer has a hole therein and a second conductive structure is disposed under the bottom of the hole. A method for forming the chip package is also provided.

Abstract: A thin-film transistor (TFT) and a manufacturing method thereof, an array substrate and a display device are provided. The TFT includes: a base substrate; a gate electrode and a gate insulating layer, disposed on the base substrate; and an active layer, wherein the gate insulating layer is disposed between the active layer and the gate electrode; the active layer includes a channel region and a doped region disposed on at least one side of the channel region; and the gate insulating layer is provided with a protrusion which is disposed between the doped region and the gate electrode.