Abstract: A memory device having a 3D structure provides MFMIS-FET memory cells with a high chip area density. The memory device includes a stack of memory cell layers interleaved with insulating layers. Channel vias penetrate through the stack. Channels of the memory cells are disposed in the channel vias. MFM portions of memory cells are sandwiched between the insulating layers in areas lateral to the channel vias. The MFM portions may be radially distributed from the channel vias and include a floating gate, a ferroelectric layer, and a gate electrode. The gate electrodes associated with a plurality of MFM structures may be united into a word line gate. The ferroelectric layer may wrap around the word line gate, whereby the ferroelectric layer is disposed above and below the word line gate as well as between the word line gate and each of the floating gates.

Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

Abstract: An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high ? dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer, a first floating gate electrode, a first control gate electrode, an erase gate electrode, and a blocking layer. The semiconductor substrate has a first source/drain region. The first semiconductor layer extends upward from the first source/drain region of the semiconductor substrate. The first floating gate electrode surrounds the first semiconductor layer. The first control gate electrode surrounds the first floating gate electrode and the first semiconductor layer. The erase gate electrode is over the first floating gate electrode and the first control gate electrode. The erase gate electrode surrounds the first semiconductor layer. The blocking layer has a first portion between the first floating gate electrode and the first control gate electrode and a second portion between the erase gate electrode and the first semiconductor layer.

Abstract: A memory cell, an integrated circuit and method of manufacturing the same are provided. The memory device includes a substrate, gate layers and insulating layers, an isolation column, a channel layer, a first conductive feature, a second conductive feature, a storage layer and a pair of isolation structures. The isolation column extends through the gate layers and the insulating layers along a first direction. The channel layer laterally covers the isolation column. The first conductive feature and second conductive feature extend along the first direction and adjacent to the isolation column. The storage layer is disposed between the gate layers and the channel layer. The pair of isolation structures extends along the first direction. The pair of isolation structures includes a first isolation structure disposed between the first conductive feature and the gate layers, and a second isolation structure disposed between the second conductive feature and the gate layers.

Abstract: A resonance detection system includes a vibration simulation mechanism and a vibration audio analysis device. The vibration simulation mechanism includes a mechanism body that accommodates a peripheral interface device, such as a notebook computer key input mechanical structure. The vibration simulation mechanism generates a vibration wave to the peripheral interface device generates a vibration audio signal in response to the vibration wave. The vibration simulation mechanism further includes a patch-type audio collector, such as a miniature auscultation radio patch, which is connected with the vibration audio analysis device. The patch-type audio collector is attached on the mechanism body containing the peripheral interface device. The vibration audio signal is collected by the patch-type audio collector.

Abstract: A semiconductor device includes a semiconductor layer, a drift region, a source area, a well region, a drain area, and a dielectric film. The drift region and the source area are formed in the semiconductor layer. The well region is formed in the semiconductor layer and between the drift region and the source area. The drain area is formed in the drift region. The dielectric film is formed in the drift region and is located between the source area and the drain area. The dielectric film includes a proximate end portion and a distal end portion which are proximate to and distal from the source area, respectively, and which are asymmetrical to each other.

Abstract: A method of forming a memory device is provided. The method comprises: forming a first storage portion on a substrate; forming a conductive layer on the first storage portion, wherein the conductive layer has a first surface coupled to the first storage portion; and forming a second storage portion on a second surface of the conductive layer, wherein the second surface is opposite to the first surface.

Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

Abstract: An anti-fuse memory cell includes a substrate, a gate dielectric layer over the substrate, a word line gate over the gate dielectric layer, a first implant region on a first side of the word line gate, a bit line contact plug over the first implant region, a second implant region on a second side of the word line gate opposite the first side of the word line gate, an oxidized region on the second implant region and having a convex upper surface and a source line gate over the convex upper surface of the oxidized region.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a substrate. The substrate includes a metal layer, a device layer disposed over the metal layer, and an insulating layer disposed vertically between the metal layer and the device layer. A semiconductor device is disposed on the device layer. An interlayer dielectric (ILD) layer is disposed over the semiconductor device and the substrate.

Abstract: A resonance detection system includes a vibration simulation mechanism and a vibration audio analysis device. The vibration simulation mechanism includes a mechanism body that accommodates a peripheral interface device. The vibration simulation mechanism generates a vibration wave to the peripheral interface device. The peripheral interface device generates a vibration audio signal in response to the vibration wave. The vibration audio analysis device is electrically connected with the vibration simulation mechanism. After the vibration audio signal is inputted into the vibration audio analysis device, the vibration audio analysis device judges whether there is an abnormal resonance phenomenon in the vibration audio signal. The vibration simulation mechanism further includes a patch-type audio collector, which is electrically connected with the vibration audio analysis device. The patch-type audio collector is attached on the mechanism body containing the peripheral interface device.

Abstract: A semiconductor isolation structure includes a handle layer, a buried insulation layer, a semiconductor layer, a deep trench isolation structure, and a heavy doping region. The buried insulation layer is disposed on the handle layer. The semiconductor layer is disposed on the buried insulation layer and has a doping type. The semiconductor layer has a functional area in which doped regions of a semiconductor device are to be formed. The deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional area. The heavy doping region is formed in the semiconductor layer, is disposed between the functional area and the deep trench isolation structure, and is surrounded by the deep trench isolation structure. The heavy doping region has the doping type. A doping concentration of the heavy doping region is higher than that of the semiconductor layer.

Abstract: A method for fabricating a semiconductor device is provided. The method includes depositing a first dielectric layer over a substrate; depositing a sacrificial layer over the first dielectric layer; depositing a second dielectric layer over the sacrificial layer; depositing an erase gate electrode layer over the second dielectric layer; etching a memory hole in the erase gate electrode layer, the sacrificial layer, and the first and second dielectric layers; and forming a semiconductor layer in the memory hole.

Abstract: An unmanned ground vehicle (UGV) includes one or more motors configured to drive one or more wheels of the UGV, a memory storing instructions, and a processor coupled to the one or more motors and the memory. The processor is configured to execute the instructions to cause the UGV to determine location information of a movable target; calculate a direction and a speed for the unmanned ground vehicle based on the determined location information; and drive the one or more motors to move the unmanned ground vehicle in the calculated direction at the calculated speed to follow the movable target when the movable target moves.

Abstract: A semiconductor isolation structure includes a handle layer, a buried insulation layer, a semiconductor layer, a deep trench isolation structure, and a heavy doping region. The buried insulation layer is disposed on the handle layer. The semiconductor layer is disposed on the buried insulation layer and has a doping type. The semiconductor layer has a functional area in which doped regions of a semiconductor device are to be formed. The deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional area. The heavy doping region is formed in the semiconductor layer, is disposed between the functional area and the deep trench isolation structure, and is surrounded by the deep trench isolation structure. The heavy doping region has the doping type. A doping concentration of the heavy doping region is higher than that of the semiconductor layer.

Abstract: A device is disclosed herein. The device includes at least two transmit portions and at least one contact portion. Each of the at least two transmit portions is configured to receive a bit line signal. The at least one contact portion is couple to the at least two transmit portions respectively and configured to transmit the bit line signals from the least two transmit portions to a source line.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

Abstract: A tool detector including a right-angle triangular base and an automatic controller is revealed. A light source of the right-angle triangular base emits a main light ray to a plane mirror to generate a reflected light ray which is incident to a quadrant detector to create a light receiving area. The automatic controller is for measuring a tool length and a tool radius. A control device of a computer numerical control machine tool sets up a standard value by a standard bar and drives an unfinished tool and a processed tool to set up an original value set and a measured value set. The automatic controller performs an error analysis on the original and measured value sets to get a relative difference of a tool length and radius of the processed tool for measuring the tool length and radius and compensation of thermal variables of the CNC machine tool.

Abstract: A transmission and distribution system with electric shock protection function includes a transmitting terminal and a receiving terminal. The transmitting terminal includes a switch, a current measurer, a signal generator, and a controller. The receiving terminal includes a filter. The switch is coupled to a first DC power and a transmission line. The current measurer is coupled to the transmission line, and measures a current of the transmission line and provides a current signal. The signal generator provides a disturbance signal to the transmission line. The controller receives the current signal and controls the switch. If the controller determines that the current signal contains the disturbance signal, the controller turns off the switch.