Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

Abstract: An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high ? dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate.

Abstract: A method for programming a memory device is provided. The memory device includes first to fourth memory cells, in which the first and second memory cells share a first erase gate, and the third and fourth memory cells share a second erase gate. The method includes applying a first voltage to control gates of the first and third memory cell; applying a second voltage to control gates of the second and fourth memory cells, in which the first voltage is higher than the second voltage; applying a third voltage to a select gate of the first memory cell; and applying a fourth voltage to select gates of the second to fourth memory cell, in which the third voltage is higher than the fourth voltage.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

Abstract: A memory device includes: a conductive layer coupled to a reference voltage level; a first storage portion vertically coupled to a first surface of the conductive layer; and a second storage portion vertically coupled to a second surface of the conductive layer; wherein the second surface is opposite to the first surface.

Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

Abstract: A tracking-distance-measuring system capable of tracking a torso object is provided. The tracking-distance-measuring system includes: an image sensor, a controller, a distance-measuring device, and an actuator device. The image sensor is configured to capture an input image. The controller is configured to analyze the input image to recognize a torso object from the input image, and calculate an offset distance between a center of the torso object and a central axis of the input image. The actuator device is configured to carry the distance-measuring device. The controller controls the actuator device to calibrate an offset angle between the distance-measuring device and the recognized torso object according to the offset distance. In response to calibrating the offset angle, the distance-measuring device emits energy and receives reflected energy to detect an object distance of the torso object.

Abstract: A tracking and ranging system includes a thermal sensor device, a controller, a ranging device and a transmission device. The thermal sensor device is configured to capture a thermal image. The controller analyzes the thermal image to identify the main heat source from among the heat sources displayed in the thermal image, and obtain an offset distance between the center points of the main heat source and the thermal image. The ranging device is coupled to the controller. The transmission device loads the ranging device and is coupled to the controller. The controller controls the motion of the transmission device in accordance with the offset distance to correct the offset angle between the ranging device and the object corresponding to the main heat source. After correcting the offset angle, the ranging device detects a first distance to the object by transmitting energy and receiving reflected energy.

Abstract: A membrane circuit board includes a first flexible circuit board, a second flexible circuit board and a nanomaterial layer. The nanomaterial layer includes plural polymeric structures. The nanomaterial layer is formed on the first flexible circuit board, the second flexible circuit board and/or a junction region between the edge of the first flexible circuit board and the second flexible circuit board to prevent at least one of the upper metallic conductor line and the lower metallic conductor line from contacting with a specified chemical element. Consequently, the conductive impedance of the upper metallic conductor line and the lower metallic conductor line is not affected by the specified chemical element. Moreover, the present invention also provides a keyboard device with the membrane circuit board.

Abstract: A keyboard device includes keyboard device includes a membrane circuit board, a base plate and a key structure. The key structure includes a keycap, a connecting element, an elastic element and a buffering structure. The connecting element is arranged between the base plate and the keycap. The elastic element is arranged between the keycap and the membrane circuit board. The buffering structure is disposed on a bottom surface of the keycap. While the keycap is depressed, the buffering structure collides with the elastic element or the connecting element. Consequently, the buffering structure provides a buffering effect.

Abstract: A keyboard device includes keyboard device includes a membrane circuit board, a base plate and a key structure. The key structure includes a keycap, a connecting element, an elastic element and a buffering structure. The connecting element is arranged between the base plate and the keycap. The elastic element is arranged between the keycap and the membrane circuit board. The buffering structure is disposed on a bottom surface of the keycap. While the keycap is depressed, the buffering structure collides with the elastic element or the connecting element. Consequently, the buffering structure provides a buffering effect.

Abstract: A membrane circuit board includes a first flexible circuit board, a second flexible circuit board and a nanomaterial layer. The nanomaterial layer includes plural polymeric structures. The nanomaterial layer is formed on the first flexible circuit board, the second flexible circuit board and/or a junction region between the edge of the first flexible circuit board and the second flexible circuit board to prevent at least one of the upper metallic conductor line and the lower metallic conductor line from contacting with a specified chemical element. Consequently, the conductive impedance of the upper metallic conductor line and the lower metallic conductor line is not affected by the specified chemical element. Moreover, the present invention also provides a keyboard device with the membrane circuit board.

Abstract: A sound control method includes following steps. Firstly, a controller commands a first ultrasonic transmitter to emit a first ultrasonic wave. Then, in a first time interval, the controller records a first received signal waveform received by an ultrasonic receiver. Then, the controller commands a second ultrasonic transmitter to emit a second ultrasonic wave. Then, in a second time interval, the controller records a second received signal waveform received by the ultrasonic receiver. Then, a playing mode of at least one speaker is controlled according to the first received signal waveform and the second received signal waveform.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

Abstract: A sound control method includes following steps. Firstly, a controller commands a first ultrasonic transmitter to emit a first ultrasonic wave. Then, in a first time interval, the controller records a first received signal waveform received by an ultrasonic receiver. Then, the controller commands a second ultrasonic transmitter to emit a second ultrasonic wave. Then, in a second time interval, the controller records a second received signal waveform received by the ultrasonic receiver. Then, a playing mode of at least one speaker is controlled according to the first received signal waveform and the second received signal waveform.

Abstract: An environment detection method includes the following steps is provided. Firstly, an ultrasonic wave is emitted to a first reflecting cone by an ultrasonic transmitter, wherein the ultrasonic wave is reflected to the environment by the first reflecting cone in a full circumferential direction. Then, the ultrasonic waves reflected back from a second reflecting cone is received by an ultrasonic receiver. Then, a received signal waveform received by the ultrasonic receiver is recorded by a controller.

Abstract: A thin film transistor and a preparation method thereof, an array substrate and a display apparatus are provided. The preparation method includes an operation of forming a low temperature poly silicon active layer; a substrate has a first region and a second region; and the step includes: forming a buffer layer on the first region and the second region of the substrate, the buffer layer having a thickness at a portion corresponding to the first region greater than that at a portion corresponding to the second region; or, forming the buffer layer on the first region of the substrate; forming an amorphous silicon layer on the buffer layer; performing laser crystallization processing on the amorphous silicon layer so as to convert the amorphous silicon layer into a poly silicon layer; and removing the poly silicon layer on the second region, and forming the low temperature poly silicon active layer on the first region.

Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

Abstract: An unmanned ground vehicle (UGV) includes one or more motors configured to drive one or more wheels of the UGV, a memory storing instructions, and a processor coupled to the one or more motors and the memory. The processor is configured to execute the instructions to cause the UGV to determine location information of a movable target; calculate a direction and a speed for the unmanned ground vehicle based on the determined location information; and drive the one or more motors to move the unmanned ground vehicle in the calculated direction at the calculated speed to follow the movable target when the movable target moves.

Abstract: An unmanned ground vehicle (UGV) includes one or more motors configured to drive one or more wheels of the UGV, an obstacle sensor, a memory storing instructions, and a processor coupled to the one or more motors, the obstacle sensor, and the memory. The processor is configured to execute the instructions to cause the UGV to obtain location information of multiple navigation points; calculate a navigation path based on the obtained location information; drive the one or more motors to navigate the UGV along the navigation path; detect, by the obstacle sensor, whether one or more obstacles exist while navigating the UGV, and if detected, determine location information of the one or more obstacles; and if the one or more obstacles are detected by the obstacle sensor, update the navigation path based on determined location information of the one or more obstacles.