Abstract: One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to devices with channel extension regions and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; and a channel below the gate structure, the channel comprising: a first channel region, adjacent to the source region; and a second channel region, adjacent to the drain region and comprising a lower threshold voltage than the first channel region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to virtual drains for decreased harmonic generation in fully depleted SOI (FDSOI) RF switches and methods of manufacture. The structure includes one or more active devices on a semiconductor on insulator material which is on top of a substrate; and a virtual drain region composed of a well region within the substrate and spaced apart from an active region of the one or more devices, the virtual drain region configured to be biased to collect electrons which would accumulate in the substrate.

Abstract: Structures for switches and methods for forming structures that include a switch. A first well and a section well are arranged in a substrate. Trench isolation regions are arranged in the substrate to define multiple active device regions. Each of the active device regions includes a section of the first well that is surrounded by the trench isolation regions. The second well has an opposite conductivity type from the first well. The active device regions and the trench isolation regions are arranged between the top surface of the substrate and the second well, and the second well is contiguous with the trench isolation regions.

Abstract: Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.

Abstract: One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts.

Abstract: The method includes prior to depositing a gate on a first vertical FET on a semiconductor substrate, depositing a first layer on the first vertical FET on the semiconductor substrate. The method further includes prior to depositing a gate on a second vertical FET on the semiconductor substrate, depositing a second layer on the second vertical FET on the semiconductor substrate. The method further includes etching the first layer on the first vertical FET to a lower height than the second layer on the second vertical FET. The method further includes depositing a gate material on both the first vertical FET and the second vertical FET. The method further includes etching the gate material on both the first vertical FET and the second vertical FET to a co-planar height.

Abstract: One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts.

Abstract: Disclosed is a semiconductor structure that includes a vertical field effect transistor (VFET) with a U-shaped semiconductor body. The semiconductor structure can be a standard VFET or a feedback VFET. In either case, the VFET includes a lower source/drain region, a semiconductor body on the lower source/drain region, and an upper source/drain region on the top of the semiconductor body. Rather than having an elongated fin shape, the semiconductor body folds back on itself in the Z direction so as to be essentially U-shaped (as viewed from above). Using a U-shaped semiconductor body reduces the dimension of the VFET in the Z direction without reducing the end-to-end length of the semiconductor body. Thus, VFET cell height can be reduced without reducing device drive current or violating critical design rules. Also disclosed is a method of forming a semiconductor structure that includes such a VFET with a U-shaped semiconductor body.

Abstract: Disclosed is a semiconductor structure that includes a vertical field effect transistor (VFET) with a U-shaped semiconductor body. The semiconductor structure can be a standard VFET or a feedback VFET. In either case, the VFET includes a lower source/drain region, a semiconductor body on the lower source/drain region, and an upper source/drain region on the top of the semiconductor body. Rather than having an elongated fin shape, the semiconductor body folds back on itself in the Z direction so as to be essentially U-shaped (as viewed from above). Using a U-shaped semiconductor body reduces the dimension of the VFET in the Z direction without reducing the end-to-end length of the semiconductor body. Thus, VFET cell height can be reduced without reducing device drive current or violating critical design rules. Also disclosed is a method of forming a semiconductor structure that includes such a VFET with a U-shaped semiconductor body.

Abstract: Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.

Abstract: The method includes prior to depositing a gate on a first vertical FET on a semiconductor substrate, depositing a first layer on the first vertical FET on the semiconductor substrate. The method further includes prior to depositing a gate on a second vertical FET on the semiconductor substrate, depositing a second layer on the second vertical FET on the semiconductor substrate. The method further includes etching the first layer on the first vertical FET to a lower height than the second layer on the second vertical FET. The method further includes depositing a gate material on both the first vertical FET and the second vertical FET. The method further includes etching the gate material on both the first vertical FET and the second vertical FET to a co-planar height.

Abstract: A semiconductor structure including a first substantially U-shaped and/or H-shaped channel is disclosed. The semiconductor structure may further include a second substantially U-shaped and/or H-shaped channel positioned above the first channel. A method of forming a substantially U-shaped and/or H-shaped channel is also disclosed. The method may include forming a fin structure on a substrate where the fin structure includes an alternating layers of sacrificial semiconductor and at least one silicon layer or region. The method may further include forming additional silicon regions vertically on sidewalls of the fin structure. The additional silicon regions may contact the silicon layer or region of the fin structure to form the substantially U-shaped and/or H-shaped channel(s). The method may further include removing the sacrificial semiconductor layers and forming a gate structure around the substantially U-shaped and/or substantially H-shaped channels.

Abstract: A vertical transport fin field effect transistor (VTFET) with a smaller cross-sectional area at the top of the fin than at the bottom, including, a substrate, a vertical fin on the substrate, wherein the vertical fin has a cross-sectional area at the base of the vertical fin that is larger than a cross-sectional area at the top of the vertical fin, wherein the cross-sectional area at the top of the vertical fin is in the range of about 10% to about 75% of the cross-sectional area at the base of the vertical fin, and a central gated region between the base and the top of the vertical fin.

Abstract: A semiconductor structure including a first substantially U-shaped and/or H-shaped channel is disclosed. The semiconductor structure may further include a second substantially U-shaped and/or H-shaped channel positioned above the first channel. A method of forming a substantially U-shaped and/or H-shaped channel is also disclosed. The method may include forming a fin structure on a substrate where the fin structure includes an alternating layers of sacrificial semiconductor and at least one silicon layer or region. The method may further include forming additional silicon regions vertically on sidewalls of the fin structure. The additional silicon regions may contact the silicon layer or region of the fin structure to form the substantially U-shaped and/or H-shaped channel(s). The method may further include removing the sacrificial semiconductor layers and forming a gate structure around the substantially U-shaped and/or substantially H-shaped channels.

Abstract: Techniques relate to forming a vertical field effect transistor (FET). One or more fins are formed on a bottom source or drain of a substrate, and one or more fins extend in a vertical direction. Gate material is formed to be positioned on sides of the one or more fins. Gate encapsulation material is formed on sides of the gate material to form a trench, such that top portions of the one or more fins are exposed in the trench. A top source or drain is formed on top of the one or more fins such that the top source or drain is laterally confined by the trench in a lateral direction that is parallel to the one or more fins.

Abstract: Various embodiments relate to gate-all-around (GAA) transistors and methods of forming such transistors. In some embodiments, a method performed on a precursor structure includes selectively removing a sacrificial nanosheet to open a vertical gap between a pair of semiconductor nanosheets; forming a first work function metal to surround the precursor nanosheet stack and fin, the first work function metal filling the vertical gap between the pair of semiconductor nano sheets; selectively removing first work function metal surrounding the fin while preserving an entirety of first work function metal surrounding the nanosheet stack; and forming a second work function metal: over a remaining portion of the first work function metal on nanosheet stack, and surrounding the fin, where first work function metal includes a different material than second work function metal.

Abstract: Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.

Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a semiconductor fin; a gate dielectric positioned above a first region of the semiconductor fin; a spacer positioned above a second region of the semiconductor fin and adjacent to the gate dielectric; and a source/drain region contacting a third region of the semiconductor fin; wherein the first region of the semiconductor fin includes substantially vertical sidewalls, and the third region of the semiconductor fin includes sloped sidewalls.

Abstract: A vertical transport fin field effect transistor (VTFET) with a smaller cross-sectional area at the top of the fin than at the bottom, including, a substrate, a vertical fin on the substrate, wherein the vertical fin has a cross-sectional area at the base of the vertical fin that is larger than a cross-sectional area at the top of the vertical fin, wherein the cross-sectional area at the top of the vertical fin is in the range of about 10% to about 75% of the cross-sectional area at the base of the vertical fin, and a central gated region between the base and the top of the vertical fin.