Abstract: Embodiments of the invention are directed to a semiconductor structure that includes a first fin structure having a first sidewall, a first gate structure adjacent a lower portion of the first sidewall, and a first spacer structure over the first gate structure and adjacent an upper portion of first the sidewall. The first spacer structure includes a first spacer structure thickness dimension that extends in a first direction away from the first sidewall. The first gate structure includes a first gate structure thickness dimension that extends in the first direction away from the first sidewall. The first gate structure dimension is about equal to the first spacer structure thickness dimension.

Abstract: Various embodiments provide systems, computer program products and computer implemented methods. In some embodiments, a system includes a computer-implemented method of determining a laterally diffuse dopant profile in semiconductor structures by providing first and second semiconductor structures having plurality of gate array structures in a silicided region separated from each other by a first distance and second distance. A potential difference is applied across the plurality of gate array structures and resistances are determined. A linear-regression fit is performed on measured resistance versus the first distance and the second distance with an extrapolated x equals 0 and a y-intercept to determine a laterally diffused dopant-profile under the plurality of gate array structures based on a semiconductor device model.

Abstract: Disclosed are performance-enhanced vertical devices (e.g., vertical field effect transistors (FETs) or complementary metal oxide semiconductor (CMOS) devices, which incorporate vertical FETs) and methods of forming such devices. A strained dielectric layer is positioned laterally adjacent to the gate of a vertical FET, increasing the charge carrier mobility within the channel region and improving performance. In a vertical n-type FET (NFET), the strain is compressive to improve electron mobility given the direction of current within the vertical NFET; whereas, in a vertical p-type FET (PFET), the strain is tensile to improve hole mobility given the direction of current within the vertical PFET. Optionally, the orientation of a vertical FET relative to the surface plane of the semiconductor wafer on which it is formed is also preplanned as function of the type of FET (i.e., NFET or PFET) for optimal charge carrier mobility and, thereby enhanced performance.

Abstract: The disclosure relates generally to a metal-oxide-semiconductor field effect transistor (MOSFET) structures and methods of forming the same. The MOSFET structure includes at least one semiconductor body on a substrate; a dielectric cap on a top surface of the at least one semiconductor body, wherein a width of the at least one semiconductor body is less than a width of the dielectric cap; a gate dielectric layer conformally coating the at least one semiconductor body; and at least one electrically conductive gate on the gate dielectric layer.

Abstract: Techniques relate to forming a vertical field effect transistor (FET). One or more fins are formed on a bottom source or drain of a substrate, and one or more fins extend in a vertical direction. Gate material is formed to be positioned on sides of the one or more fins. Gate encapsulation material is formed on sides of the gate material to form a trench, such that top portions of the one or more fins are exposed in the trench. A top source or drain is formed on top of the one or more fins such that the top source or drain is laterally confined by the trench in a lateral direction that is parallel to the one or more fins.

Abstract: An integrated circuit having a reference device and method of forming the same. A reference device is disclosed having: a fully depleted n-type MOSFET implemented as a long channel device having a substantially undoped body; and a fully depleted p-type MOSFET implemented with as a long channel device having a substantially undoped body; wherein the n-type MOSFET and p-type MOSFET are connected in series and employ identical gate stacks, wherein each has a gate electrically coupled to a respective drain to form two diodes, and wherein both diodes are in one of an on state and an off state according to a value of an electrical potential applied across the n-type MOSFET and p-type MOSFET.

Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance.

Abstract: One aspect of the disclosure provides for a method of forming a replacement gate structure. The method may include: removing a dummy gate from over a set of fins to form an opening in a dielectric layer exposing the set of fins, each fin in the set of fins being substantially separated from an adjacent fin in the set of fins via an dielectric; forming a protective cap layer within the opening over the exposed set of fins; removing a portion of the dielectric on each side of each fin in the set of fins; undercutting each fin by removing a portion of each fin in the set of fins to create a notch disposed under the protective cap layer; substantially filling each notch with an oxide; forming a gate dielectric over each fin in the set of fins; and forming a gate conductor over the gate dielectric, thereby forming the replacement gate structure.

Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance.

Abstract: Disclosed are field effect transistor (FET) formation methods using a final gate cut process and the resulting structures. One method forms an elongated gate across first and second semiconductor bodies for first and second FETs, respectively. An opening is formed in a portion of the elongated gate between the semiconductor bodies, cutting at least the gate conductor layer. The opening is filled with an isolation layer, thereby forming an isolation region that segments the elongated gate into first and second gates for the first and second FETs, respectively. Another method forms at least three gates across an elongated semiconductor body. An isolation region is formed that extends, not only through a portion of a center one of the gates, but also through a corresponding portion of the elongated semiconductor body adjacent to that gate, thereby segmenting the elongated semiconductor body into discrete semiconductor bodies for first and second FETs.

Abstract: A semiconductor device includes a plurality of vertical-transport fin field effect transistors that are arranged at a locally-variable fin pitch. Within a first region of the device, a first plurality of fins are arranged at a first pitch (d1), and within a second region of the device, a second plurality of fins are arranged as a second pitch (d2) less than the first pitch. The second plurality of fins share merged source, drain and gate regions, while the source, drain and gate regions for the first plurality of fins are unmerged.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to multi-finger devices in multiple-gate-contacted-pitch, integrated structures and methods of manufacture. The structure includes: a first plurality of fin structures formed on a substrate having a channel surface in a {110} plane; and a second plurality of fin structures formed on the substrate with a channel surface in a {100} plane, positioned in relation to the first plurality of fin structures.

Abstract: A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.

Abstract: Embodiments of the present invention are directed to a method of forming a conductive via. The method includes forming an opening in a substrate and forming a conductive material along sidewall regions of the opening, wherein the conductive material occupies a first portion of an area within the opening. The method further includes forming an insulating fill in a second portion of the area within the opening, wherein at least one surface of the conductive material and at least one surface of the insulating fill are substantially coplanar with a front surface of the substrate.

Abstract: The present invention relates generally to integrated circuits and more particularly, to a structure and method of forming a hybrid circuit including a tunnel field-effect transistor (TFET) and a conventional field effect transistor (FET). Embodiments of the present invention include a hybrid amplifier which features a TFET common-source feeding a common-gate conventional FET (e.g. a MOSFET). A TFET gate may be electrically isolated from an output from a conventional FET. Thus, a high impedance input may be received by a TFET with a high-isolation output (i.e. low capacitance) at a conventional FET. A hybrid circuit amplifier including a TFET and a conventional FET may have a very high input impedance and a low miller capacitance.

Abstract: Logic circuits, or logic gates, are disclosed comprising vertical transport field effect transistors and one or more active gates, wherein the number of CPP's for the logic circuit, in isolation, is equal to the number of active gates. The components of the logic circuit can be present in at least three different vertical circuit levels, including a circuit level comprising at least one horizontal plane passing through a conductive element that provides an input voltage to the one or more gate structures and another conductive element that provides an output voltage of the logic circuit, and another circuit level that comprises a horizontal plane passing through a conductive bridge from the N output to P output of the field effect transistors. Such logic circuits can include single-gate inverters, two-gate inverters, NOR2 logic gates, and NAND3 logic gates, among other more complicated logic circuits.

Abstract: One aspect of the disclosure provides for a method of forming a replacement gate structure. The method may include: removing a dummy gate from over a set of fins to form an opening in a dielectric layer exposing the set of fins, each fin in the set of fins being substantially separated from an adjacent fin in the set of fins via an dielectric; forming a protective cap layer within the opening over the exposed set of fins; removing a portion of the dielectric on each side of each fin in the set of fins; undercutting each fin by removing a portion of each fin in the set of fins to create a notch disposed under the protective cap layer; substantially filling each notch with an oxide; forming a gate dielectric over each fin in the set of fins; and forming a gate conductor over the gate dielectric, thereby forming the replacement gate structure.

Abstract: One embodiment provides a method comprising etching a fin of a fin-shaped field effect transistor (FinFET) to form a reduced fin, and laterally etching the reduced fin to form a fin channel including a first fin channel sidewall and a second fin channel sidewall opposing the first fin channel sidewall. The method further comprises forming a first thin dielectric tunnel and a second thin dielectric tunnel on the first fin channel sidewall and the second fin channel sidewall, respectively. Each thin dielectric tunnel prevents lateral epitaxial crystal growth on the fin channel. The method further comprises etching an insulator layer disposed between the fin channel and a substrate of the FinFET to expose portions of a substrate surface of the substrate. A source epitaxy and a drain epitaxy are formed from vertical epitaxial crystal growth on the exposed portions of the substrate surface after epitaxial deposition.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.

Abstract: A method of forming a via and a wiring structure formed are disclosed. The method may include forming a conductive line in a first dielectric layer; forming a hard mask adjacent to the conductive line after the conductive line forming; forming a second dielectric layer over the hard mask; and forming a via opening to the conductive line in the second dielectric layer. The via opening lands at least partially on the hard mask to self-align the via opening to the conductive line. A via may be formed by filling the via opening with a conductor.