Patents by Inventor Hiroyuki Kanaya

Hiroyuki Kanaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10043852
    Abstract: According to one embodiment, a magnetoresistive memory device includes first electrodes located in an interlayer insulating film, second electrodes located on the respective first electrodes within the interlayer insulating film, magnetoresistive effect elements on the respective second electrodes, and third electrodes on the respective magnetoresistive effect elements. The first electrodes and the second electrodes are displaced from each other.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: August 7, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroyuki Kanaya
  • Patent number: 9887237
    Abstract: According to an embodiment, a magnetic storage device includes a semiconductor region including a trench; a gate electrode disposed in the trench; an insulation film covering the gate electrode and provided in a manner to fill the trench; and a magnetoresistive effect element including at least a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer, the non-magnetic layer in a side surface of the magnetoresistive effect element including the non-magnetic layer being provided on a top surface of the insulation film.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: February 6, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shintaro Sakai, Keisuke Nakatsuka, Hiroyuki Kanaya, Yoshinori Kumura, Katsuyuki Fujita
  • Publication number: 20170141157
    Abstract: According to an embodiment, a magnetic storage device includes a semiconductor region including a trench; a gate electrode disposed in the trench; an insulation film covering the gate electrode and provided in a manner to fill the trench; and a magnetoresistive effect element including at least a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer, the non-magnetic layer in a side surface of the magnetoresistive effect element including the non-magnetic layer being provided on a top surface of the insulation film.
    Type: Application
    Filed: March 9, 2016
    Publication date: May 18, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shintaro SAKAI, Keisuke NAKATSUKA, Hiroyuki KANAYA, Yoshinori KUMURA, Katsuyuki FUJITA
  • Publication number: 20170047375
    Abstract: According to one embodiment, a magnetoresistive memory device includes first electrodes located in an interlayer insulating film, second electrodes located on the respective first electrodes within the interlayer insulating film, magnetoresistive effect elements on the respective second electrodes, and third electrodes on the respective magnetoresistive effect elements. The first electrodes and the second electrodes are displaced from each other.
    Type: Application
    Filed: March 11, 2016
    Publication date: February 16, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroyuki KANAYA
  • Publication number: 20160308115
    Abstract: According to one embodiment, a magnetoresistive memory device includes bottom electrodes provided on a substrate, a magnetoresistive element provided on each of the bottom electrodes, a top electrode provided on each of the magnetoresistive elements, an insulating film provided on sides of the bottom electrode, the magnetoresistive element and, the top electrode, and a magnetic layer provided on the top electrode, the magnetic layer extending on the insulating film to connect a plurality of those of the top electrodes.
    Type: Application
    Filed: March 10, 2016
    Publication date: October 20, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroyuki KANAYA
  • Patent number: 9306152
    Abstract: According to one embodiment, a magnetic memory is disclosed. The magnetic memory includes an underlying structure having conductivity provided on the substrate and including a first layer with a polycrystalline structure and a second layer with an amorphous structure, and a magnetoresistive element provide on the underlying layer. The magnetoresistive element includes a first magnetic layer provided on the underlying layer, a non-magnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the non-magnetic layer.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: April 5, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayoshi Iwayama, Hiroyuki Kanaya
  • Publication number: 20160072045
    Abstract: According to one embodiment, a magnetic memory is disclosed. The magnetic memory comprises an interconnect layer, a first conductive layer on the interconnect layer, the first conductive layer including a metal, an oxide layer on the first conductive layer, a second conductive layer on the oxide layer, a magnetoresistive element on the second conductive layer, the magnetoresistive element including a first magnetic layer, a second magnetic layer and a nonmagnetic layer between the first and second magnetic layers, and a deposited material on a sidewall of the oxide layer, the deposited material including the metal.
    Type: Application
    Filed: January 9, 2015
    Publication date: March 10, 2016
    Inventors: Hiroyuki KANAYA, Hisanori AIKAWA, Keisuke NAKATSUKA
  • Patent number: 9276195
    Abstract: According to one embodiment, a magnetic random access memory includes a magnetoresistive element, a contact arranged under the magnetoresistive element and connected to the magnetoresistive element, and an insulating film continuously formed from a periphery of the contact to a side surface of the magnetoresistive element and including a protective portion covering the side surface of the magnetoresistive element.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: March 1, 2016
    Inventors: Hiroyuki Kanaya, Kuniaki Sugiura
  • Patent number: 9171886
    Abstract: A semiconductor memory device according to embodiments includes a semiconductor substrate and plural switching transistors provided on the semiconductor substrate. In the semiconductor memory device, a contact plug is embedded between adjacent two of the switching transistors, and is insulated from gates of the adjacent two switching transistors. The contact plug is also electrically connected to a source or a drain of each of the adjacent two switching transistors, and an upper surface of the contact plug is at a position higher than an upper surface of the switching transistors. A memory element is provided on the upper surface of the contact plug and stores data. A wiring is provided on the memory element.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: October 27, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyuki Kanaya, Yukinori Koyama, Susumu Shuto, Kuniaki Sugiura
  • Publication number: 20150263267
    Abstract: One embodiment discloses a magnetic memory. The magnetic memory includes a substrate, an electrode provided on the substrate, a member provided on the electrode and having an amorphous structure, and a magnetoresistive element provided on the member. The magnetoresistive element is located within a closed curve defining a contour of an upper surface of the member.
    Type: Application
    Filed: September 9, 2014
    Publication date: September 17, 2015
    Inventor: Hiroyuki KANAYA
  • Publication number: 20150255706
    Abstract: According to one embodiment, a magnetic memory is disclosed. The magnetic memory includes an underlying structure having conductivity provided on the substrate and including a first layer with a polycrystalline structure and a second layer with an amorphous structure, and a magnetoresistive element provide on the underlying layer. The magnetoresistive element includes a first magnetic layer provided on the underlying layer, a non-magnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the non-magnetic layer.
    Type: Application
    Filed: July 2, 2014
    Publication date: September 10, 2015
    Inventors: Masayoshi IWAYAMA, Hiroyuki KANAYA
  • Patent number: 9105572
    Abstract: According to one embodiment, a magnetic memory includes a cell transistor including a first source/drain diffusion layer and a second source/drain diffusion layer, a first contact on the first source/drain diffusion layer, a memory element on the first contact, and a second contact on the second source/drain diffusion layer, the second contact including a first plug on the second source/drain diffusion layer, and a second plug on the first plug.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: August 11, 2015
    Inventors: Hiroyuki Kanaya, Dong Jun Kim, Sung Hoon Lee
  • Patent number: 9076720
    Abstract: An aspect of the present embodiment, there is provided magnetic random access memory device including a semiconductor substrate, a selection transistor on the semiconductor substrate, the selection transistor including a diffusion layer, a contact plug on diffusion layer, an amorphous film on the contact plug, a lower electrode provided on the amorphous film, a first magnetic layer, a nonmagnetic layer, a second magnetic layer, an upper electrode stacked in an order and a sidewall contact film on the contact plug, the sidewall contact film being in contact with a sidewall of the upper electrode.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: July 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Kanaya
  • Publication number: 20150069480
    Abstract: According to one embodiment, a magnetic memory includes a cell transistor including a first source/drain diffusion layer and a second source/drain diffusion layer, a first contact on the first source/drain diffusion layer, a memory element on the first contact, and a second contact on the second source/drain diffusion layer, the second contact including a first plug on the second source/drain diffusion layer, and a second plug on the first plug.
    Type: Application
    Filed: March 10, 2014
    Publication date: March 12, 2015
    Inventors: Hiroyuki KANAYA, Dong Jun KIM, Sung Hoon LEE
  • Patent number: 8969983
    Abstract: A memory includes a semiconductor substrate. Cell transistors are on the substrate. Contact plugs each of which is buried between the adjacent cell transistors and electrically connected to a diffusion layer between the adjacent cell transistors. An interlayer dielectric film buries gaps between the contact plugs. A storage element is provided not above the contact plugs but above the interlayer dielectric film. A sidewall film covers a part of a side surface of the storage element, and is provided to overlap with one of the contact plugs as viewed from above a surface of the semiconductor substrate. A lower electrode is provided between a bottom of the storage element and the interlayer dielectric film and between the sidewall film and one of the contact plugs, and electrically connects the storage element to one of the contact plugs.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: March 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Kanaya
  • Publication number: 20140284734
    Abstract: According to one embodiment, a magnetic random access memory includes a magnetoresistive element, a contact arranged under the magnetoresistive element and connected to the magnetoresistive element, and an insulating film continuously formed from a periphery of the contact to a side surface of the magnetoresistive element and including a protective portion covering the side surface of the magnetoresistive element.
    Type: Application
    Filed: August 12, 2013
    Publication date: September 25, 2014
    Inventors: Hiroyuki KANAYA, Kuniaki SUGIURA
  • Patent number: 8786038
    Abstract: A semiconductor storage device according to the present embodiment includes a selection element formed on a surface of a semiconductor substrate. A lower electrode is connected to the selection element. A magnetic tunnel junction element is provided on the lower electrode. An upper electrode is provided on the magnetic tunnel junction element. A growth layer is provided on the upper electrode and is composed of a conductive material and has a larger area than the upper electrode when viewed from above the surface of the semiconductor substrate. A wiring line is provided on the growth layer.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: July 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Hosotani, Hiroyuki Kanaya
  • Publication number: 20140097477
    Abstract: An aspect of the present embodiment, there is provided magnetic random access memory device including a semiconductor substrate, a selection transistor on the semiconductor substrate, the selection transistor including a diffusion layer, a contact plug on diffusion layer, an amorphous film on the contact plug, a lower electrode provided on the amorphous film, a first magnetic layer, a nonmagnetic layer, a second magnetic layer, an upper electrode stacked in an order and a sidewall contact film on the contact plug, the sidewall contact film being in contact with a sidewall of the upper electrode.
    Type: Application
    Filed: October 10, 2013
    Publication date: April 10, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Kanaya
  • Patent number: 8592928
    Abstract: According to one embodiment, a magnetic random access memory includes a selection element formed on a semiconductor substrate, an interlayer dielectric film formed above the selection element, a contact layer formed in the interlayer dielectric film, and electrically connected to the selection element, a lower electrode layer made of a metal material, and electrically connected to the contact layer, a metal oxide insulating film made of an oxide of the metal material, and surrounding a side surface of the lower electrode layer, a magnetoresistive element formed on the lower electrode layer, an upper electrode layer formed on the magnetoresistive element, a sidewall insulating film formed on a side surface of the magnetoresistive element and a side surface of the upper electrode layer, and a bit line electrically connected to the upper electrode layer.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: November 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Hosotani, Hiroyuki Kanaya, Takeshi Kajiyama
  • Publication number: 20130015541
    Abstract: A memory includes a semiconductor substrate. Cell transistors are on the substrate. Contact plugs each of which is buried between the adjacent cell transistors and electrically connected to a diffusion layer between the adjacent cell transistors. An interlayer dielectric film buries gaps between the contact plugs. A storage element is provided not above the contact plugs but above the interlayer dielectric film. A sidewall film covers a part of a side surface of the storage element, and is provided to overlap with one of the contact plugs as viewed from above a surface of the semiconductor substrate. A lower electrode is provided between a bottom of the storage element and the interlayer dielectric film and between the sidewall film and one of the contact plugs, and electrically connects the storage element to one of the contact plugs.
    Type: Application
    Filed: March 20, 2012
    Publication date: January 17, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroyuki KANAYA