Abstract: An aspect of the present embodiment, there is provided magnetic random access memory device including a semiconductor substrate, a selection transistor on the semiconductor substrate, the selection transistor including a diffusion layer, a contact plug on diffusion layer, an amorphous film on the contact plug, a lower electrode provided on the amorphous film, a first magnetic layer, a nonmagnetic layer, a second magnetic layer, an upper electrode stacked in an order and a sidewall contact film on the contact plug, the sidewall contact film being in contact with a sidewall of the upper electrode.

Abstract: A semiconductor storage device according to the present embodiment includes a selection element formed on a surface of a semiconductor substrate. A lower electrode is connected to the selection element. A magnetic tunnel junction element is provided on the lower electrode. An upper electrode is provided on the magnetic tunnel junction element. A growth layer is provided on the upper electrode and is composed of a conductive material and has a larger area than the upper electrode when viewed from above the surface of the semiconductor substrate. A wiring line is provided on the growth layer.

Abstract: According to one embodiment, a magnetic random access memory includes a selection element formed on a semiconductor substrate, an interlayer dielectric film formed above the selection element, a contact layer formed in the interlayer dielectric film, and electrically connected to the selection element, a lower electrode layer made of a metal material, and electrically connected to the contact layer, a metal oxide insulating film made of an oxide of the metal material, and surrounding a side surface of the lower electrode layer, a magnetoresistive element formed on the lower electrode layer, an upper electrode layer formed on the magnetoresistive element, a sidewall insulating film formed on a side surface of the magnetoresistive element and a side surface of the upper electrode layer, and a bit line electrically connected to the upper electrode layer.

Abstract: A semiconductor memory device according to the present embodiment includes a semiconductor substrate, a select transistor, a lower electrode, a magnetic tunnel junction element, a first protection film, an upper electrode, and a second protection film. The select transistor is formed on the semiconductor substrate. The lower electrode is electrically connected to one diffusion layer of the select transistor. The magnetic tunnel junction element is provided on the lower electrode. The first protection film is provided on a side surface of the magnetic tunnel junction element. The upper electrode is provided on the magnetic tunnel junction element and the first protection film. The second protection film is provided on side surfaces of the upper electrode, the first protection film, and the lower electrode.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of transistors connected in series and including a transistor having first and second diffusion regions arranged in the semiconductor substrate. The device also includes an insulating film columnar body arranged above the semiconductor substrate, and having a side which is inclined to a top surface of the substrate by an inclination angle greater than 0 degrees and less than 90 degrees. The device includes a memory cell including a first electrode arranged on the side of the insulating film columnar body and connected to the first diffusion region via a first contact plug, a ferroelectric film arranged on the first electrode, and a second electrode arranged on the ferroelectric film, and connected to the second diffusion region via a second contact plug.

Abstract: A semiconductor memory device according to embodiments includes a semiconductor substrate and plural switching transistors provided on the semiconductor substrate. In the semiconductor memory device, a contact plug is embedded between adjacent two of the switching transistors, and is insulated from gates of the adjacent two switching transistors. The contact plug is also electrically connected to a source or a drain of each of the adjacent two switching transistors, and an upper surface of the contact plug is at a position higher than an upper surface of the switching transistors. A memory element is provided on the upper surface of the contact plug and stores data. A wiring is provided on the memory element.

Abstract: A semiconductor memory device includes a plurality of transistors on a semiconductor substrate; a first interlayer dielectric film on the transistors; a plurality of ferroelectric capacitors on the first interlayer dielectric film; a first hydrogen barrier film covering an upper surface and a side surface of each of the ferroelectric capacitors; a second interlayer dielectric film above the ferroelectric capacitors, the second interlayer dielectric film being buried to have a void or hole between two adjacent ferroelectric capacitors out of the ferroelectric capacitors; a cover dielectric film covering the second interlayer dielectric film to close an opening of the void or hole; and a second hydrogen barrier film covering the cover dielectric film.

Abstract: A first electrode film, a ferroelectric film, and a second electrode film are accumulated above a semiconductor in this order, a hard mask is accumulated above the second electrode, scrub cleaning is performed on the surface of the hard mask with an surfactant, the hard mask on which the scrub cleaning is performed has been patterned according to a planar shape of a ferroelectric capacitor, and etching is performed by using as a hard mask the hard mask that has been patterned.

Abstract: According to an aspect of the present invention, there is provided a semiconductor memory device comprising, a first transistor and a second transistor formed on a semiconductor substrate, a memory capacitor formed above the first transistor, the memory capacitor being connected to the first transistor, a dummy memory capacitor formed above the second transistor, a wiring layer formed above the memory capacitor and the dummy memory capacitor, the wiring layer being connected to the first transistor and the memory capacitor, a first plug connecting between the second transistor and the dummy memory capacitor, and a second plug connecting between the dummy memory capacitor and the wiring layer.

Abstract: According to one embodiment, a semiconductor memory device having a ferroelectric film, includes a semiconductor substrate, a field effect transistor formed on the semiconductor substrate, an inter-layer insulating film formed on the field effect transistor and the semiconductor substrate, a plug constituted with a single-crystalline structure, the plug being formed in the inter-layer insulating film and being connected with a source or a drain of the field effect transistor, a lower electrode constituted with a single-crystalline structure formed on the plug, a ferroelectric film formed on the lower electrode an upper electrode formed on the ferroelectric film.

Abstract: According to an aspect of the present invention, there is provided a semiconductor apparatus including a semiconductor substrate, a transistor formed on the semiconductor substrate, an insulating film disposed on the semiconductor substrate, a ferroelectric capacitor and an upper mask. The ferroelectric capacitor includes a lower electrode disposed on the insulating film, a ferroelectric film disposed on the lower electrode and an upper electrode disposed on the ferroelectric film. The upper mask includes a hard mask disposed on the upper electrode and a sidewall mask disposed on at least part of a sidewall of the hard mask.

Abstract: A semiconductor memory device includes a switching transistor provided on a semiconductor substrate; an interlayer dielectric film on the switching transistor; a contact plug in the interlayer dielectric film; a ferroelectric capacitor above the contact plug and the interlayer dielectric film, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode; a diffusion layer in the semiconductor substrate, the diffusion layer electrically connecting the contact plug to the switching transistor; a hydrogen barrier film on a side surface of the ferroelectric capacitor; and an interconnection comprising a TiN film or a TiAlxNy film entirely covering up an upper surface of the upper electrode and contacting with the upper surface of the upper electrode.

Abstract: A first electrode film, a ferroelectric film, and a second electrode film are accumulated above a semiconductor in this order, a hard mask is accumulated above the second electrode, scrub cleaning is performed on the surface of the hard mask with an surfactant, the hard mask on which the scrub cleaning is performed has been patterned according to a planar shape of a ferroelectric capacitor, and etching is performed by using as a hard mask the hard mask that has been patterned.

Abstract: A semiconductor memory device including a ferroelectric capacitor, the ferroelectric capacitor includes a lower electrode having a plurality of protrusions; a ferroelectric film on the lower electrode, the ferroelectric film having a plurality of protrusions engaging with the protrusions of the lower electrode; and an upper electrode on the ferroelectric film, the upper electrode having a plurality of protrusions engaging with the protrusions of the lower electrode.

Abstract: According to an aspect of the present invention, there is provided a semiconductor device, including: a semiconductor substrate; a transistor that is formed on the semiconductor substrate; an interlayer insulating film that is formed on the semiconductor substrate so as to cover the transistor and that has a through hole formed thereinside so as to reach the transistor; a plug lower-electrode that is formed in the through hole and that is connected to the transistor; a ferroelectric film that is formed on the plug lower-electrode; and an upper-electrode that is formed on the ferroelectric film.

Abstract: A non-volatile memory device including a ferroelectric capacitor is disclosed. A method of manufacturing a non-volatile memory device including a ferroelectric capacitor is also disclosed. A first electrode is formed on an insulating film provided on a semiconductor substrate. A first ferroelectric film is formed on the first electrode. The first ferroelectric film has a convexo-concave surface portion. A second ferroelectric film is formed on the first ferroelectric film so as to bury the convexo-concave surface portion. The second ferroelectric film has a surface flatter than that of the first ferroelectric film. A second electrode is formed on the second ferroelectric film. A protective film is formed at least on a portion of an upper surface of the second electrode. The protective film serves as a barrier against hydrogen.

Abstract: A ferroelectric memory device includes a top electrode, a bottom electrode, a ferroelectric film which is sandwiched between the top and bottom electrodes, includes a first portion having a side surface flushed with a side surface of the top electrode and a second portion having a side surface flushed with a side surface of the bottom electrode, and has a step formed by making the side surface of the second portion project outward from the side surface of the first portion, a top mask which is provided on the top electrode, and a side mask which is provided on part of a side surface of the top mask, the side surfaces of the top electrode and the first portion of the ferroelectric film and has a top at a lower level than a top of the top mask and at a higher level than a top of the top electrode.

Abstract: A semiconductor memory device includes a semiconductor substrate; a ferroelectric capacitor comprising an upper electrode, a ferroelectric film, and a lower electrode above the semiconductor substrate; and an upper interlayer dielectric film surrounding a periphery of the ferroelectric capacitor, wherein a gap is provided between the ferroelectric capacitor and the upper interlayer dielectric film.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of transistors connected in series and including a transistor having first and second diffusion regions arranged in the semiconductor substrate. The device also includes an insulating film columnar body arranged above the semiconductor substrate, and having a side which is inclined to a top surface of the substrate by an inclination angle greater than 0 degrees and less than 90 degrees. The device includes a memory cell including a first electrode arranged on the side of the insulating film columnar body and connected to the first diffusion region via a first contact plug, a ferroelectric film arranged on the first electrode, and a second electrode arranged on the ferroelectric film, and connected to the second diffusion region via a second contact plug.

Abstract: A semiconductor device has a first interlayer insulating film formed on a semiconductor substrate, a first plug and a second plug embedded in holes formed to open the first interlayer insulating film, a capacitor formed on the first interlayer insulating film so as to connect to the first plug, a hydrogen barrier film including an aluminum oxynitride material and formed so as to cover the capacitor, the first interlayer insulating film and the second plug, a second interlayer insulating film formed on the hydrogen barrier film, a third plug embedded in a hole formed so as to open the second interlayer insulating film and the hydrogen barrier film and expose an upper surface of the upper electrode, and a fourth plug embedded in a hole formed so as to open the second interlayer insulating film and the hydrogen barrier film and expose an upper surface of the second plug.