Patents by Inventor Hiroyuki Kanaya

Hiroyuki Kanaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080067567
    Abstract: According to an aspect of the present invention, there is provided a semiconductor device including: a substrate; an insulating film disposed on the substrate; a plug electrode disposed in the insulating film; and a capacitor unit including: a lower electrode that is disposed on the insulating film and that covers a top face of the plug electrode, a ferroelectric film disposed on the lower electrode, a first upper electrode disposed on the ferroelectric film, and a second upper electrode disposed on the ferroelectric film and separated from the first upper electrode; wherein the first upper electrode covers a center of the plug electrode as viewed in a direction perpendicular to a surface of the semiconductor substrate.
    Type: Application
    Filed: September 12, 2007
    Publication date: March 20, 2008
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kanaya, Iwao Kunishima
  • Patent number: 7339218
    Abstract: A semiconductor memory device includes a semiconductor substrate having a first region and a second region, a transistor placed in the first region of the semiconductor substrate, a first insulating film formed on the semiconductor substrate in the first and second regions and on the transistor, a first ferroelectric capacitor formed on the first insulating film in the first region and electrically connected to the transistor, a hydrogen barrier film formed above the first ferroelectric capacitor and above the first insulating film in the first and second regions, a first contact penetrating the hydrogen barrier film in the first region and electrically connected to the first ferroelectric capacitor, and a second contact which penetrates the hydrogen barrier film in the second region and which is in a floating state.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: March 4, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Hidaka, Iwao Kunishima, Hiroyuki Kanaya
  • Publication number: 20070231948
    Abstract: A method of manufacturing a semiconductor device, including forming a capacitor above a semiconductor substrate, the capacitor including a dielectric film containing Pb, Zr, Ti and O. Forming the capacitor includes forming a crystallized film which contains Pb, Sr, Zr, Ti, Ru and O.
    Type: Application
    Filed: May 25, 2007
    Publication date: October 4, 2007
    Applicant: KABUSHHIKI KAISHA TOSHIBA
    Inventors: Keisuke Nakazawa, Koji Yamakawa, Katsuaki Natori, Soichi Yamazaki, Hiroshi Itokawa, Hiroyuki Kanaya
  • Patent number: 7259094
    Abstract: An apparatus for manufacturing a semiconductor device is disclosed which comprises a chamber which holds a to-be-processed substrate having a film containing at least one kind of metal element which will become a component of a volatile metal compound, a heater which heats the substrate held in the chamber, and an adsorbent which is provided in the chamber and which adsorbs the volatile metal compound generated from the film by heating the substrate.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: August 21, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Natori, Keisuke Nakazawa, Koji Yamakawa, Hiroyuki Kanaya, Yoshinori Kumura, Hiroshi Itokawa, Osamu Arisumi
  • Patent number: 7233040
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, and a capacitor provided above the semiconductor substrate and including a film which contains Pb, Sr, Zr, Ti, Ru and O and a dielectric film which contains Pb, Zr, Ti and O and which is provided on the film containing Pb, Sr, Zr, Ti, Ru and O.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: June 19, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keisuke Nakazawa, Koji Yamakawa, Katsuaki Natori, Soichi Yamazaki, Hiroshi Itokawa, Hiroyuki Kanaya
  • Publication number: 20070077721
    Abstract: A semiconductor device comprising a capacitive element which is provided above the semiconductor substrate and which has a capacitive insulation film held between an upper electrode and a lower electrode, a conductor for upper electrode which is connected to the upper electrode, a side-wall adsorbent member which covers a side wall of the conductor for upper electrode and which is composed of a material that adsorbs at least hydrogen, a conductor for lower electrode which is connected to the lower electrode, and a first adsorbent member which is provided at least either between the conductor for upper electrode and the capacitive insulation film or between the conductor for lower electrode and the capacitive insulation film, and which is composed of a material that adsorbs at least hydrogen.
    Type: Application
    Filed: December 2, 2005
    Publication date: April 5, 2007
    Inventor: Hiroyuki Kanaya
  • Patent number: 7190015
    Abstract: A semiconductor device including a semiconductor substrate, a capacitor formed above the semiconductor substrate, a first interlayer insulating film formed above the capacitor and having a trench, a wiring formed above the capacitor and formed in the trench, the wiring have a top surface flush with a top surface of the first interlayer insulating film, a first hydrogen barrier film formed in contact with the top surface of the wiring and the top surface of the first interlayer insulating film and preventing hydrogen from diffusing into the capacitor and a second interlayer insulating film formed on the first hydrogen barrier film.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: March 13, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Natori, Koji Yamakawa, Hiroyuki Kanaya
  • Publication number: 20070052065
    Abstract: A semiconductor device comprising a substrate and a ferroelectric capacitor formed on the substrate. The ferroelectric capacitor includes a lower electrode, an upper electrode and a ferroelectric film interposed between the lower and upper electrodes. The ferroelectric capacitor having sidewalls receded from sidewalls of the upper electrode.
    Type: Application
    Filed: March 22, 2006
    Publication date: March 8, 2007
    Inventor: Hiroyuki Kanaya
  • Publication number: 20060244022
    Abstract: According to an aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate, a capacitor which is disposed above the semiconductor substrate and in which a dielectric film is held between lower and upper electrodes, an oxide film formed in such a manner as to coat the capacitor and having a thickness of 5 nm or more and 50 nm or less, and a protective film formed on the oxide film by an ALD process.
    Type: Application
    Filed: June 30, 2005
    Publication date: November 2, 2006
    Inventors: Katsuaki Natori, Hiroyuki Kanaya, Koji Yamakawa
  • Publication number: 20060244023
    Abstract: A ferroelectric memory device includes a top electrode, a bottom electrode, a ferroelectric film which is sandwiched between the top and bottom electrodes, includes a first portion having a side surface flushed with a side surface of the top electrode and a second portion having a side surface flushed with a side surface of the bottom electrode, and has a step formed by making the side surface of the second portion project outward from the side surface of the first portion, a top mask which is provided on the top electrode, and a side mask which is provided on part of a side surface of the top mask, the side surfaces of the top electrode and the first portion of the ferroelectric film and has a top at a lower level than a top of the top mask and at a higher level than a top of the top electrode.
    Type: Application
    Filed: March 14, 2006
    Publication date: November 2, 2006
    Inventor: Hiroyuki KANAYA
  • Patent number: 7095068
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first transistor formed on the semiconductor substrate and including a first gate electrode and first and second diffusion layers, a first contact connected to the first diffusion layer, a first conductive oxygen barrier film electrically connected to the first contact and covering at least the upper surface of the first contact, a first ferroelectric capacitor including a first electrode, a second electrode, and a first ferroelectric film interposed between the first and second electrodes, and a first connecting member connected to the first electrode and to the first conductive oxygen barrier film.
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: August 22, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Kumura, Iwao Kunishima, Tohru Ozaki, Hiroyuki Kanaya, Shinichi Watanabe
  • Publication number: 20060180894
    Abstract: A semiconductor memory device, which prevents the penetration of hydrogen or moisture to a ferroelectric capacitor from its surrounding area including a contact plug portion, comprises a ferroelectric capacitor formed above a semiconductor substrate, a first hydrogen barrier film formed on an upper surface of the ferroelectric capacitor to work as a mask in the formation of the ferroelectric capacitor, a second hydrogen barrier film formed on the upper surface and a side face of the ferroelectric capacitor including on the first hydrogen barrier film, and a contact plug disposed through the first and second hydrogen barrier films, and connected to an upper electrode of the ferroelectric capacitor, a side face thereof being surrounded with the hydrogen barrier films.
    Type: Application
    Filed: June 2, 2005
    Publication date: August 17, 2006
    Inventors: Yoshinori Kumura, Iwao Kunishima, Hiroyuki Kanaya, Tohru Ozaki, Kazuhiro Tomioka
  • Patent number: 7091538
    Abstract: A semiconductor device comprises a semiconductor substrate including a diffusion area, a capacitor provided above the semiconductor substrate and including a lower electrode, a dielectric film, and an upper electrode, a plug provided between the semiconductor substrate and the capacitor and having a lower end connected to the diffusion area and an upper end connected to the lower electrode, and a dummy plug provided between the semiconductor substrate and the capacitor and having a lower end not connected to the diffusion area and an upper end connected to the lower electrode.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: August 15, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Natori, Koji Yamakawa, Hiroyuki Kanaya
  • Publication number: 20060175645
    Abstract: A semiconductor device includes a switching element formed on a semiconductor substrate, a first interconnect layer formed on the semiconductor substrate and having a first wiring connected to one terminal of the switching element, a ferroelectric capacitor formed on the first interconnect layer and having a first electrode connected to the one terminal of the switching element via the first wiring, a first protective film formed on the ferroelectric capacitor and the first interconnect layer, a second interconnect layer formed on the first protective film and having a second wiring connected to a second electrode of the ferroelectric capacitor and a first interlayer insulating film having a dielectric constant of 4 or more, and a third interconnect layer formed on the second interconnect layer and having a second interlayer insulating film with a dielectric constant of less than 4.
    Type: Application
    Filed: March 13, 2006
    Publication date: August 10, 2006
    Inventors: Hiroyuki Kanaya, Iwao Kunishima
  • Patent number: 7045837
    Abstract: The present invention provides a ferroelectric device relatively free of fences by using a hardmask having high etching selectivity relative to an underlying barrier layer. The present invention also includes a method for suppressing the fences clinging to the sidewalls of ferroelectric devices. Additionally, the present invention provides a ferroelectric device having a hardmask relatively thin compared to an underlying barrier layer when compared to prior art devices.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: May 16, 2006
    Assignees: Infineon Technologies AG, Kabushiki Kaisha Toshiba
    Inventors: Ulrich Egger, Haoren Zhuang, Yoshinoru Kumura, Kazuhiro Tomioka, Hiroyuki Kanaya
  • Publication number: 20060071258
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a dielectric film provided on the bottom electrode, and a top electrode provided on the dielectric film, a mask film provided on the top electrode and used as a mask when a pattern of the capacitor is formed, wherein an inclination of a side surface of the mask film is gentler than an inclination of a side surface of the top electrode and an inclination of a side surface of the dielectric film.
    Type: Application
    Filed: October 12, 2004
    Publication date: April 6, 2006
    Inventors: Kazuhiro Tomioka, Tomoaki Ishida, Masatoshi Fukushima, Masanobu Baba, Hiroyuki Kanaya, Haoren Zhuang
  • Patent number: 7022531
    Abstract: A semiconductor memory device including a memory cell block having a plurality of memory transistors formed on a semiconductor substrate. The memory transistors include first and second impurity-diffused regions and a gate formed therebetween. A plurality of memory cells are also included in the memory cell block and have lower electrodes connected to the first impurity-diffused regions, ferroelectric films formed on the lower electrodes and first upper electrodes formed on the ferroelectric films and connected to the second impurity-diffused regions. Further included are block selecting transistors formed on the semiconductor substrate and being connected to one end of the memory cell block. Second upper electrodes are also formed adjoined to the block selecting transistors and being disconnected from the first upper electrode of the memory cells.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: April 4, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tohru Ozaki, Iwao Kunishima, Toyota Morimoto, Hiroyuki Kanaya
  • Patent number: 7001780
    Abstract: A ferroelectric device includes a bottom electrode on which are formed ferrocapacitor elements and, over the ferroelectric elements, top electrodes. The bottom electrodes are connected to lower layers of the device via conductive plugs, and the plugs and bottom electrodes are spaced apart by barrier elements of Ir and/or IrO2. The barrier elements are narrower than the bottom electrode elements, and are formed by a separate etching process. This means that Ir fences are not formed during the etching of the bottom electrode. Also, little Ir and/or IrO2 diffuses through the bottom electrode to the ferroelectric elements, and therefore there is little risk of damage to the ferroelectric material.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: February 21, 2006
    Assignees: Infineon Technologies AG, Kabushiki Kaisha Toshiba
    Inventors: Haoren Zhuang, Ulrich Egger, Jingyu Lian, Stefan Gernhardt, Hiroyuki Kanaya
  • Publication number: 20060017086
    Abstract: There is provided a semiconductor device having a ferroelectric capacitor formed on a semiconductor substrate covered with an insulator film, wherein the ferroelectric capacitor comprises: a bottom electrode formed on the insulator film; a ferroelectric film formed on the bottom electrode; and a top electrode formed on the ferroelectric film. The ferroelectric film has a stacked structure of either of two-layer-ferroelectric film or three-layer-ferroelectric film. The upper ferroelectric film is metallized and prevents hydrogen from diffusing in lower ferroelectric layer. Crystal grains of the stacked ferroelectric films are preferably different.
    Type: Application
    Filed: September 13, 2005
    Publication date: January 26, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kanaya, Iwao Kunishima, Koji Yamakawa, Tsuyoshi Iwamoto, Hiroshi Mochizuki, Yoshinori Kumura
  • Patent number: 6982444
    Abstract: There is provided a semiconductor device having a ferroelectric capacitor formed on a semiconductor substrate covered with an insulator film, wherein the ferroelectric capacitor comprises: a bottom electrode formed on the insulator film; a ferroelectric film formed on the bottom electrode; and a top electrode formed on the ferroelectric film. The ferroelectric film has a stacked structure of either of two-layer-ferroelectric film or three-layer-ferroelectric film. The upper ferroelectric film is metallized and prevents hydrogen from diffusing in lower ferroelectric layer. Crystal grains of the stacked ferroelectric films are preferably different.
    Type: Grant
    Filed: May 22, 2003
    Date of Patent: January 3, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kanaya, Iwao Kunishima, Koji Yamakawa, Tsuyoshi Iwamoto, Hiroshi Mochizuki, Yoshinori Kumura