Patents by Inventor Hiroyuki Kanaya

Hiroyuki Kanaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7573120
    Abstract: According to an aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate, a capacitor which is disposed above the semiconductor substrate and in which a dielectric film is held between lower and upper electrodes, an oxide film formed in such a manner as to coat the capacitor and having a thickness of 5 nm or more and 50 nm or less, and a protective film formed on the oxide film by an ALD process.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: August 11, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Natori, Hiroyuki Kanaya, Koji Yamakawa
  • Publication number: 20090134440
    Abstract: A semiconductor device comprising a substrate and a ferroelectric capacitor formed on the substrate. The ferroelectric capacitor includes a lower electrode, an upper electrode and a ferroelectric film interposed between the lower and upper electrodes. The ferroelectric capacitor having sidewalls receded from sidewalls of the upper electrode.
    Type: Application
    Filed: January 29, 2009
    Publication date: May 28, 2009
    Inventor: Hiroyuki KANAYA
  • Patent number: 7531408
    Abstract: A method of manufacturing a semiconductor device, including forming a capacitor above a semiconductor substrate, the capacitor including a dielectric film containing Pb, Zr, Ti and O. Forming the capacitor includes forming a crystallized film which contains Pb, Sr, Zr, Ti, Ru and O.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: May 12, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keisuke Nakazawa, Koji Yamakawa, Katsuaki Natori, Soichi Yamazaki, Hiroshi Itokawa, Hiroyuki Kanaya
  • Publication number: 20090095994
    Abstract: A semiconductor device comprises a substrate; an insulating layer formed over the substrate; a contact hole formed through the insulating layer; a plurality of first plug electrodes each formed inside the contact hole to the surface of the insulating layer; a capacitor layer formed on the first plug electrode in a first region; and a second plug electrode formed on the first plug electrode in a second region different from the first region. The capacitor layer includes a lower electrode, a ferroelectric film, and an upper electrode stacked in turn. The first plug electrode includes a plug conduction layer formed from the surface of the substrate, and a plug barrier layer formed from above the plug conduction layer up to an upper surface of the insulating layer, the plug barrier layer having a higher etching selection ratio than the lower electrode.
    Type: Application
    Filed: October 14, 2008
    Publication date: April 16, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyuki Kanaya, Yoshinori Kumura
  • Patent number: 7508020
    Abstract: A semiconductor device comprising a substrate and a ferroelectric capacitor formed on the substrate. The ferroelectric capacitor includes a lower electrode, an upper electrode and a ferroelectric film interposed between the lower and upper electrodes. The ferroelectric capacitor having sidewalls receded from sidewalls of the upper electrode.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: March 24, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Kanaya
  • Patent number: 7504684
    Abstract: A semiconductor device comprising a capacitive element which is provided above the semiconductor substrate and which has a capacitive insulation film held between an upper electrode and a lower electrode, a conductor for upper electrode which is connected to the upper electrode, a side-wall adsorbent member which covers a side wall of the conductor for upper electrode and which is composed of a material that adsorbs at least hydrogen, a conductor for lower electrode which is connected to the lower electrode, and a first adsorbent member which is provided at least either between the conductor for upper electrode and the capacitive insulation film or between the conductor for lower electrode and the capacitive insulation film, and which is composed of a material that adsorbs at least hydrogen.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: March 17, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Kanaya
  • Patent number: 7501675
    Abstract: A semiconductor device according to an aspect of the present invention comprises a semiconductor substrate, a ferroelectric capacitor, a protective film and an auxiliary capacitor. The ferroelectric capacitor is provided above the semiconductor substrate and comprises an upper electrode, a lower electrode and a ferroelectric film interposed between the upper and lower electrodes. The protective film is formed, covering the ferroelectric capacitor. The auxiliary capacitor is provided in a circuit section peripheral to the ferroelectric capacitor and uses the protective film as capacitor insulating film.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: March 10, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Natori, Soichi Yamazaki, Koji Yamakawa, Hiroyuki Kanaya
  • Publication number: 20080277704
    Abstract: This disclosure concerns a semiconductor device comprising a switching transistor provided on a semiconductor substrate; an interlayer dielectric film formed on the switching transistor; a ferroelectric capacitor including an upper electrode, a ferroelectric film, and a lower electrode formed on the interlayer dielectric film; a contact plug provided within the interlayer dielectric film and electrically connected to the lower electrode; a diffusion layer connected to between the contact plug and the switching transistor; a barrier metal covering a whole upper surface of the upper electrode; and an insulation sidewall film provided on a side surface of the barrier metal and provided substantially on a same plane as a side surface of the upper electrode.
    Type: Application
    Filed: April 28, 2008
    Publication date: November 13, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroyuki KANAYA
  • Patent number: 7446362
    Abstract: A semiconductor memory device includes a semiconductor substrate having a first region and a second region, a transistor placed in the first region of the semiconductor substrate, a first insulating film formed on the semiconductor substrate in the first and second regions and on the transistor, a first ferroelectric capacitor formed on the first insulating film in the first region and electrically connected to the transistor, a hydrogen barrier film formed above the first ferroelectric capacitor and above the first insulating film in the first and second regions, a first contact penetrating the hydrogen barrier film in the first region and electrically connected to the first ferroelectric capacitor, and a second contact which penetrates the hydrogen barrier film in the second region and which is in a floating state.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: November 4, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Hidaka, Iwao Kunishima, Hiroyuki Kanaya
  • Patent number: 7429508
    Abstract: A semiconductor memory device includes a semiconductor substrate having a first region and a second region, a transistor placed in the first region of the semiconductor substrate, a first insulating film formed on the semiconductor substrate in the first and second regions and on the transistor, a first ferroelectric capacitor formed on the first insulating film in the first region and electrically connected to the transistor, a hydrogen barrier film formed above the first ferroelectric capacitor and above the first insulating film in the first and second regions, a first contact penetrating the hydrogen barrier film in the first region and electrically connected to the first ferroelectric capacitor, and a second contact which penetrates the hydrogen barrier film in the second region and which is in a floating state.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: September 30, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Hidaka, Iwao Kunishima, Hiroyuki Kanaya
  • Publication number: 20080217669
    Abstract: According to an aspect of the present invention, there is provided a semiconductor memory device comprising, a first transistor and a second transistor formed on a semiconductor substrate, a memory capacitor formed above the first transistor, the memory capacitor being connected to the first transistor, a dummy memory capacitor formed above the second transistor, a wiring layer formed above the memory capacitor and the dummy memory capacitor, the wiring layer being connected to the first transistor and the memory capacitor, a first plug connecting between the second transistor and the dummy memory capacitor, and a second plug connecting between the dummy memory capacitor and the wiring layer.
    Type: Application
    Filed: February 27, 2008
    Publication date: September 11, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroyuki KANAYA
  • Patent number: 7402858
    Abstract: A semiconductor memory device includes a semiconductor substrate having a first region and a second region, a transistor placed in the first region of the semiconductor substrate, a first insulating film formed on the semiconductor substrate in the first and second regions and on the transistor, a first ferroelectric capacitor formed on the first insulating film in the first region and electrically connected to the transistor, a hydrogen barrier film formed above the first ferroelectric capacitor and above the first insulating film in the first and second regions, a first contact penetrating the hydrogen barrier film in the first region and electrically connected to the first ferroelectric capacitor, and a second contact which penetrates the hydrogen barrier film in the second region and which is in a floating state.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: July 22, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Hidaka, Iwao Kunishima, Hiroyuki Kanaya
  • Patent number: 7400005
    Abstract: A semiconductor memory device, which prevents the penetration of hydrogen or moisture to a ferroelectric capacitor from its surrounding area including a contact plug portion, comprises a ferroelectric capacitor formed above a semiconductor substrate, a first hydrogen barrier film formed on an upper surface of the ferroelectric capacitor to work as a mask in the formation of the ferroelectric capacitor, a second hydrogen barrier film formed on the upper surface and a side face of the ferroelectric capacitor including on the first hydrogen barrier film, and a contact plug disposed through the first and second hydrogen barrier films, and connected to an upper electrode of the ferroelectric capacitor, a side face thereof being surrounded with the hydrogen barrier films.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: July 15, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Kumura, Iwao Kunishima, Hiroyuki Kanaya, Tohru Ozaki, Kazuhiro Tomioka
  • Publication number: 20080121956
    Abstract: According to an aspect of the invention, there is provided, a semiconductor device having a ferroelectric memory cell, comprising a semiconductor substrate, a transistor being formed on the semiconductor substrate, an inter-layer insulator being formed over the transistor to cover the transistor, a ferroelectric capacitor including a lower electrode formed over the inter-layer insulator, a ferroelectric film and a upper electrode stacked in order, and a hydrogen barrier film covering a surface including the side-wall of the ferroelectric capacitor, wherein at least a portion of a tilt of a side-wall of the lower electrode, the tilt of the side-wall of the lower electrode having an angle to an bottom surface of the lower electrode, is more gradual than a tilt of a side-wall of the upper electrode and a side-wall of the ferroelectric film continuing to the side-wall of the lower electrode.
    Type: Application
    Filed: November 19, 2007
    Publication date: May 29, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroyuki KANAYA
  • Publication number: 20080121957
    Abstract: A non-volatile memory device including a ferroelectric capacitor is disclosed. A method of manufacturing a non-volatile memory device including a ferroelectric capacitor is also disclosed. A first electrode is formed on an insulating film provided on a semiconductor substrate. A first ferroelectric film is formed on the first electrode. The first ferroelectric film has a convexo-concave surface portion. A second ferroelectric film is formed on the first ferroelectric film so as to bury the convexo-concave surface portion. The second ferroelectric film has a surface flatter than that of the first ferroelectric film. A second electrode is formed on the second ferroelectric film. A protective film is formed at least on a portion of an upper surface of the second electrode. The protective film serves as a barrier against hydrogen.
    Type: Application
    Filed: November 20, 2007
    Publication date: May 29, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroyuki KANAYA
  • Publication number: 20080073684
    Abstract: A semiconductor memory device includes a semiconductor substrate having a first region and a second region, a transistor placed in the first region of the semiconductor substrate, a first insulating film formed on the semiconductor substrate in the first and second regions and on the transistor, a first ferroelectric capacitor formed on the first insulating film in the first region and electrically connected to the transistor, a hydrogen barrier film formed above the first ferroelectric capacitor and above the first insulating film in the first and second regions, a first contact penetrating the hydrogen barrier film in the first region and electrically connected to the first ferroelectric capacitor, and a second contact which penetrates the hydrogen barrier film in the second region and which is in a floating state.
    Type: Application
    Filed: November 16, 2007
    Publication date: March 27, 2008
    Inventors: Osamu Hidaka, Iwao Kunishima, Hiroyuki Kanaya
  • Publication number: 20080076192
    Abstract: A semiconductor memory device includes a semiconductor substrate having a first region and a second region, a transistor placed in the first region of the semiconductor substrate, a first insulating film formed on the semiconductor substrate in the first and second regions and on the transistor, a first ferroelectric capacitor formed on the first insulating film in the first region and electrically connected to the transistor, a hydrogen barrier film formed above the first ferroelectric capacitor and above the first insulating film in the first and second regions, a first contact penetrating the hydrogen barrier film in the first region and electrically connected to the first ferroelectric capacitor, and a second contact which penetrates the hydrogen barrier film in the second region and which is in a floating state.
    Type: Application
    Filed: November 16, 2007
    Publication date: March 27, 2008
    Inventors: Osamu Hidaka, Iwao Kunishima, Hiroyuki Kanaya
  • Publication number: 20080073683
    Abstract: A semiconductor memory device includes a semiconductor substrate having a first region and a second region, a transistor placed in the first region of the semiconductor substrate, a first insulating film formed on the semiconductor substrate in the first and second regions and on the transistor, a first ferroelectric capacitor formed on the first insulating film in the first region and electrically connected to the transistor, a hydrogen barrier film formed above the first ferroelectric capacitor and above the first insulating film in the first and second regions, a first contact penetrating the hydrogen barrier film in the first region and electrically connected to the first ferroelectric capacitor, and a second contact which penetrates the hydrogen barrier film in the second region and which is in a floating state.
    Type: Application
    Filed: November 16, 2007
    Publication date: March 27, 2008
    Inventors: Osamu HIDAKA, Iwao Kunishima, Hiroyuki Kanaya
  • Publication number: 20080073750
    Abstract: According to an aspect of the present invention, there is provided a semiconductor storage apparatus including: a semiconductor substrate; and a ferroelectric capacitor including: a bottom electrode disposed above the semiconductor substrate, a ferroelectric layer disposed on the bottom electrode, and a top electrode disposed on the ferroelectric layer. The ferroelectric capacitor includes: a first sidewall portion located on a position where the top electrode is in contact with the ferroelectric layer, and a second sidewall portion located above the first sidewall portion. The first sidewall portion forms a first angle with a top face of the ferroelectric layer. The second sidewall portion forms a second angle with the top face. The first angle is larger than the second angle.
    Type: Application
    Filed: September 20, 2007
    Publication date: March 27, 2008
    Inventor: Hiroyuki KANAYA
  • Publication number: 20080073681
    Abstract: According to an aspect of the present invention, there is provided a semiconductor apparatus including a semiconductor substrate, a transistor formed on the semiconductor substrate, an insulating film disposed on the semiconductor substrate, a ferroelectric capacitor and an upper mask. The ferroelectric capacitor includes a lower electrode disposed on the insulating film, a ferroelectric film disposed on the lower electrode and an upper electrode disposed on the ferroelectric film. The upper mask includes a hard mask disposed on the upper electrode and a sidewall mask disposed on at least part of a sidewall of the hard mask.
    Type: Application
    Filed: September 20, 2007
    Publication date: March 27, 2008
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki KANAYA