Patents by Inventor Horng Lin
Horng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11980040Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.Type: GrantFiled: June 14, 2021Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tai-Yen Peng, Tsung-Hsien Chang, Yu-Shu Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Chung-Te Lin
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Publication number: 20240139924Abstract: An electric nail gun includes a main body unit, a hammer unit, and a motor unit. The hammer unit includes a hammer member that is adapted for striking a nail, and a resilient member that has two opposite ends respectively abutting against the hammer member and the main body unit. The resilient member of the hammer unit constantly provides a hammer restoring force for the hammer member to move in a striking direction for striking the nail. The motor unit is mounted to the main body unit, and includes a lifting wheel. The lifting wheel has at least one pushing portion that separably engages the hammer member, and that is operable to push the hammer member to move in an energy storage direction opposite to the striking direction such that the resilient member of the hammer unit is compressed and provides the hammer restoring force to the hammer member.Type: ApplicationFiled: October 31, 2023Publication date: May 2, 2024Applicant: BASSO INDUSTRY CORP.Inventors: An-Gi LIU, Chang-Sheng Lin, Guey-Horng Liou
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Patent number: 11945785Abstract: Disclosed herein are heterocyclic compounds, for example, according to the following formula and analogs thereof: that inhibit the activity of FLT3. Also described are specific covalent inhibitors of FLT3. Also disclosed are pharmaceutical compositions that include the compounds. Methods of using the FLT3 inhibitors are disclosed, alone or in combination with other therapeutic agents, for the treatment of proliferative diseases or conditions, including hematological malignancies and other diseases or conditions dependent on FLT3 activity.Type: GrantFiled: December 29, 2022Date of Patent: April 2, 2024Assignee: Biomea Fusion, Inc.Inventors: David Sperandio, Xiaodong Wang, Thorsten A. Kirschberg, James T. Palmer, Thomas Butler, Solomon B. Ungashe, Neil Howard Squires, Nan-Horng Lin, Ravindra B. Upasani, Amna Trinity-Turjuman Adam, Yongli Su, Thu Phan
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Publication number: 20240105851Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first well region and a second well region in a substrate. The method includes forming a third well region in the substrate and between the first well region and the second well region. The method includes forming a deep well region in the substrate and under the first well region and the third well region. The method includes partially removing the substrate to form a first fin, a second fin, and a third fin in the first well region, the second well region, and the third well region respectively. The method includes forming a first epitaxial structure, a second epitaxial structure, and a third epitaxial structure in the first recess, the second recess, and the third recess respectively.Type: ApplicationFiled: January 12, 2023Publication date: March 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiefeng Jeff LIN, Chen-Hua TSAI, Shyh-Horng YANG
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Patent number: 11944017Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.Type: GrantFiled: May 5, 2023Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tai-Yen Peng, Yu-Shu Chen, Chien Chung Huang, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
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Patent number: 11942550Abstract: A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.Type: GrantFiled: February 24, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Chang Su, Yan-Ting Lin, Chien-Wei Lee, Bang-Ting Yan, Chih Teng Hsu, Chih-Chiang Chang, Chien-I Kuo, Chii-Horng Li, Yee-Chia Yeo
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Publication number: 20240096958Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a fin on a substrate. A gate structure is over the fin. A source/drain is in the fin proximate the gate structure. The source/drain includes a bottom layer, a supportive layer over the bottom layer, and a top layer over the supportive layer. The supportive layer has a different property than the bottom layer and the top layer, such as a different material, a different natural lattice constant, a different dopant concentration, and/or a different alloy percent content.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Jung-Chi Tai, Chii-Horng Li, Pei-Ren Jeng, Yen-Ru Lee, Yan-Ting Lin, Chih-Yun Chin
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Publication number: 20240099150Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
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Publication number: 20240096781Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.Type: ApplicationFiled: March 20, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
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Publication number: 20240087935Abstract: A closed gas circulation system may include a sealed plenum, circulation fans, and a fan filter unit (FFU) inlet to contain, filter, condition, and re-circulate a gas through a chamber of an interface tool. The gas provided to the chamber is maintained in a conditioned environment in the closed gas circulation system as opposed to introducing external air into the chamber through the FFU inlet. This enables precise control over the relative humidity and oxygen concentration of the gas used in the chamber, which reduces the oxidation of semiconductor wafers that are transferred through the chamber. The closed gas circulation system may also include an air-flow rectifier, a return vent, and one or more vacuum pumps to form a downflow of collimated gas in the chamber and to automatically control the feed-forward pressure and flow of gas through the chamber and the sealed plenum.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Inventors: Jyh-Shiou HSU, Chyi-Tsong NI, Mu-Tsang LIN, Su-Horng LIN
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Patent number: 11914286Abstract: The present disclosure provides an apparatus for a lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame including a material selected from the group consisting of boron nitride (BN), boron carbide (BC), and a combination thereof, a mask, a first adhesive layer that secures the pellicle membrane to the pellicle frame, and a second adhesive layer that secures the pellicle frame to the mask.Type: GrantFiled: April 4, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Amo Chen, Yun-Yue Lin, Ta-Cheng Lien, Hsin-Chang Lee, Chih-Cheng Lin, Jeng-Horng Chen
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Patent number: 11854851Abstract: A closed gas circulation system may include a sealed plenum, circulation fans, and a fan filter unit (FFU) inlet to contain, filter, condition, and re-circulate a gas through a chamber of an interface tool. The gas provided to the chamber is maintained in a conditioned environment in the closed gas circulation system as opposed to introducing external air into the chamber through the FFU inlet. This enables precise control over the relative humidity and oxygen concentration of the gas used in the chamber, which reduces the oxidation of semiconductor wafers that are transferred through the chamber. The closed gas circulation system may also include an air-flow rectifier, a return vent, and one or more vacuum pumps to form a downflow of collimated gas in the chamber and to automatically control the feed-forward pressure and flow of gas through the chamber and the sealed plenum.Type: GrantFiled: March 5, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jyh-Shiou Hsu, Chyi-Tsong Ni, Mu-Tsang Lin, Su-Horng Lin
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Publication number: 20230380293Abstract: A method for fabricating magnetic tunnel junction (MTJ) pillars is provided. The method includes following operations. A MTJ stack of layers including a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer is provided. A first patterning step is carried out by using a reactive ion etching. In the first patterning step, the second magnetic layer and the tunnel barrier layer are etched to form one or more pillar structures and a protection layer is formed and covers sidewalls of the pillar structures.Type: ApplicationFiled: July 25, 2023Publication date: November 23, 2023Inventors: JIANN-HORNG LIN, KUN-YI LI, HAN-TING LIN, HUAN-JUST LIN, CHEN-JUNG WANG, SIN-YI YANG
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Patent number: 11808805Abstract: One embodiment of the present invention sets forth an integrated circuit. The integrated circuit includes a plurality of subunits associated with a plurality of operating voltages. The integrated circuit also includes one or more voltage regulator circuits that convert a first input voltage into a first plurality of output voltages during a first test, wherein the plurality of output voltages is delivered to the plurality of subunits via a plurality of output channels.Type: GrantFiled: July 27, 2022Date of Patent: November 7, 2023Assignee: NVIDIA CorporationInventors: Francisco Da Silva, Li-Wei Ko, Shang-Ju Lee, Shyh-Horng Lin
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Publication number: 20230339867Abstract: Disclosed herein are heterocyclic compounds that inhibit the activity of FLT3. Also described are specific covalent inhibitors of FLT3. Also disclosed are pharmaceutical compositions that include the compounds. Methods of using the FLT3 inhibitors are disclosed, alone or in combination with other therapeutic agents, for the treatment of proliferative diseases or conditions, including hematological malignancies and other diseases or conditions dependent on FLT3 activity.Type: ApplicationFiled: December 29, 2022Publication date: October 26, 2023Inventors: David Sperandio, Xiaodong Wang, Thorsten A. Kirschberg, James T. Palmer, Thomas Butler, Solomon B. Ungashe, Neil Howard Squires, Nan-Horng Lin, Ravindra B. Upasani, Amna Trinity-Turjuman Adam, Yongli Su, Thu Phan
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Patent number: 11770977Abstract: A method for fabricating magnetic tunnel junction (MTJ) pillars is provided. The method includes following operations. A MTJ stack of layers including a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer is provided. A first patterning step is carried out by using a reactive ion etching. In the first patterning step, the second magnetic layer and the tunnel barrier layer are etched to form one or more pillar structures and a protection layer is formed and covers sidewalk of the pillar structures.Type: GrantFiled: October 27, 2020Date of Patent: September 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jiann-Horng Lin, Kun-Yi Li, Han-Ting Lin, Huan-Just Lin, Chen-Jung Wang, Sin-Yi Yang
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Patent number: 11753170Abstract: An aircraft seat may include a seat pan cushion coupled to a seat base. The aircraft seat may include a seat back cushion. The aircraft seat may include an auxiliary rear section. The auxiliary rear section may be configured to transition between an extended position and a retracted position. The seat pan cushion and the seat back cushion may be configured to transition between a first position and a second position. The auxiliary rear section may be configured to be in the extended position when the seat pan cushion and the seat back cushion are in the first position. The auxiliary rear section may be configured to be in the retracted position when the seat pan cushion and the seat back cushion are in the second position.Type: GrantFiled: March 29, 2021Date of Patent: September 12, 2023Assignee: B/E Aerospace, Inc.Inventors: Tracy Pence, Aaron D. LaPrade, Twinkle V. Jacob, Catalin Bunea, Horng Lin
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Publication number: 20230282513Abstract: A recovery layer (e.g., a layer of organic and/or tin-based material) is formed within recesses, in which adjacent MEOL or BEOL structures are formed, after plasma ashing and before a trimming process. The recovery layer preserves hardmask material and dielectric material such that upper surfaces of the adjacent MEOL or BEOL structures remain physically separated. As a result, the adjacent MEOL or BEOL remain electrically isolated and functional.Type: ApplicationFiled: March 7, 2022Publication date: September 7, 2023Inventors: Zheng-En BAO, Po-Ju CHEN, Chih-Teng LIAO, Jiann-Horng LIN, Lin-Ting LIN
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Publication number: 20230253268Abstract: A method includes placing a wafer on a rotation mechanism of a metrology device; illuminating, by using a light source of the metrology device, the wafer by an X-ray; rotating, by using the rotation mechanism, the wafer while illuminating the wafer by the X-ray; detecting, by using an image sensor of the metrology device, a transmission portion of the X-ray passing through the wafer while rotating the wafer; and obtaining, by using a processor of the metrology device, a top width and a bottom width of a structure over the wafer based on the transmission portion of the X-ray with different rotating angles of the rotation mechanism.Type: ApplicationFiled: April 21, 2023Publication date: August 10, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Su-Horng LIN, Chi-Ming YANG
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Publication number: 20230154760Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.Type: ApplicationFiled: January 18, 2023Publication date: May 18, 2023Inventors: Jiann-Horng Lin, Cheng-Li Fan, Chih-Hao Chen