Patents by Inventor Horng Lin

Horng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230154760
    Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.
    Type: Application
    Filed: January 18, 2023
    Publication date: May 18, 2023
    Inventors: Jiann-Horng Lin, Cheng-Li Fan, Chih-Hao Chen
  • Patent number: 11652007
    Abstract: A method includes illuminating a wafer by an X-ray, detecting a spatial domain pattern produced when illuminating the wafer by the X-ray, identifying at least one peak from the detected spatial domain pattern, and analyzing the at least one peak to obtain a morphology of a transistor structure of the wafer.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Su-Horng Lin, Chi-Ming Yang
  • Patent number: 11628225
    Abstract: An antibody-drug conjugate (ADC) has a structure represented by Formula (I): a pharmaceutically acceptable salt thereof wherein Ab is an antibody without glycans (i.e., the protein portion an antibody); G1 and G2 are glycan moieties, which may be the same or different; Cn1 and Cn2 are conjugation moieties, which may be the same or different; L1 and L2 are linker moieties, which may be the same or different; D1 and D2; are drug units which may be the same or different; and x and y are independently an integer from 0 to 8, provided that x+y?0.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: April 18, 2023
    Assignee: CHO PHARMA INC.
    Inventors: Nan-Horng Lin, Charng-Sheng Tsai, Ting-Chun Hung, Hong-Yang Chuang
  • Patent number: 11626292
    Abstract: In a pattern formation method, a photo resist pattern is formed over a target layer to be patterned. An extension material layer is formed on the photo resist pattern. The target layer is patterned by using at least the extension material layer as an etching mask.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: April 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chang Lee, Jiann-Horng Lin, Chih-Hao Chen, Ying-Hao Wu, Wen-Yen Chen, Shih-Hua Tseng, Shu-Huei Suen
  • Publication number: 20230086137
    Abstract: Described herein is N-[4-[4-(4-morpholinyl)-7H-pyrrolo[2,3-d]pyrimidin-6-yl]phenyl]-4-[[3(R)-[(1-oxo-2-propen-1-yl)amino]-1-piperidinyl]methyl]-2-pyridinecarboxamide, including crystalline forms, solvates, and pharmaceutically acceptable salts thereof. Also disclosed are pharmaceutical compositions that include the compound, as well as methods of using the compound, alone or in combination with other therapeutic agents, for the treatment of autoimmune diseases or conditions, heteroimmune diseases or conditions, cancer, including lymphoma, and inflammatory diseases or conditions.
    Type: Application
    Filed: August 10, 2022
    Publication date: March 23, 2023
    Inventors: Priaynka SOMANATH, Daniel LU, Taisei KINOSHITA, Brian LAW, Thomas BUTLER, James T. PALMER, Nan-Horng LIN, Heow Meng TAN, Angelina Sau Man WONG, Siyi JAING, Hongyan HE
  • Patent number: 11594419
    Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jiann-Horng Lin, Cheng-Li Fan, Chih-Hao Chen
  • Patent number: 11545619
    Abstract: A method for forming a memory device structure is provided. The method includes providing a substrate, a first dielectric layer, a conductive via, a magnetic tunnel junction cell, a first etch stop layer, and a first spacer layer. The substrate has a first region and a second region, the first dielectric layer is over the substrate, the conductive via passes through the first dielectric layer over the first region. The method includes removing the first etch stop layer, which is not covered by the first spacer layer. The method includes removing the first dielectric layer, which is not covered by the first etch stop layer.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsing-Hsiang Wang, Han-Ting Lin, Yu-Feng Yin, Sin-Yi Yang, Chen-Jung Wang, Yin-Hao Wu, Kun-Yi Li, Meng-Chieh Wen, Lin-Ting Lin, Jiann-Horng Lin, An-Shen Chang, Huan-Just Lin
  • Publication number: 20220349056
    Abstract: Embodiments of mechanisms for processing a semiconductor wafer are provided. A method for processing a wafer includes providing a wafer process apparatus. The wafer process apparatus includes a chamber and a stage positioned in the chamber for supporting the semiconductor wafer. The method also includes supplying a process gas to the semiconductor wafer via a discharged assembly that is adjacent to the stage. The discharged assembly includes a discharged passage configured without a vertical flow path section.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 3, 2022
    Inventor: Su-Horng LIN
  • Publication number: 20220331746
    Abstract: Disclosed are a light-driven filtration antibacterial composite membrane and a preparation method and use thereof. The method for preparing the light-driven filtration antibacterial composite membrane includes: mixing dichloromethane and N,N-dimethylformamide to obtain a first solution; adding PCL particles to the first solution, and stirring until being uniform to obtain an electrospinning solution; adding a ZIF-8 powder to the electrospinning solution, and ultrasonically dispersing for at least 1 hour to obtain a PCL/ZIF-8 spinning solution; spraying the PCL/ZIF-8 spinning solution onto a PPCL@PDA/TAEG men-blown membrane to obtain the light-driven filtration antibacterial composite membrane.
    Type: Application
    Filed: April 18, 2022
    Publication date: October 20, 2022
    Applicants: Tiangong University, Minjiang University, Tianjin Yuzhan International Trade Co., Ltd.
    Inventors: Ting-Ting LI, Lu Yang, Heng Zhang, Bo Gao, Jia-Horng Lin, Ching-Wen Lou
  • Patent number: 11443959
    Abstract: A system includes a chamber, an inlet valve, a control device, and a recycle pipe. The chamber is configured to perform a semiconductor process and including an output port. The inlet valve is coupled to the chamber and a supply pipe. The controller is coupled to the inlet valve and the chamber. The recycle pipe arranged outside the chamber and coupled to the chamber. The recycle pipe is independent from the supply pipe. The controller is configured to determine whether the chamber is idle, and is configured to control the inlet valve based on the determination of whether the chamber is idle. When the controller closes the output port of the chamber and opens the inlet valve, water from the supply pipe flows into a wall of the chamber through the inlet valve first and then flows into the recycle pipe.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Su-Horng Lin
  • Publication number: 20220285192
    Abstract: A closed gas circulation system may include a sealed plenum, circulation fans, and a fan filter unit (FFU) inlet to contain, filter, condition, and re-circulate a gas through a chamber of an interface tool. The gas provided to the chamber is maintained in a conditioned environment in the closed gas circulation system as opposed to introducing external air into the chamber through the FFU inlet. This enables precise control over the relative humidity and oxygen concentration of the gas used in the chamber, which reduces the oxidation of semiconductor wafers that are transferred through the chamber. The closed gas circulation system may also include an air-flow rectifier, a return vent, and one or more vacuum pumps to form a downflow of collimated gas in the chamber and to automatically control the feed-forward pressure and flow of gas through the chamber and the sealed plenum.
    Type: Application
    Filed: March 5, 2021
    Publication date: September 8, 2022
    Inventors: Jyh-Shiou Hsu, Chyi-Tsong Ni, Mu-Tsang Lin, Su-Horng Lin
  • Publication number: 20220271087
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. A substrate having a cell region and a mark region is received. A dielectric layer is etched to expose a conductive line in the cell region and form a trench in the mark region. A conductive layer is formed over the cell region and in the trench. The conductive layer is etched to form a bottom electrode via in the cell region and a first mark layer in the trench.
    Type: Application
    Filed: February 24, 2021
    Publication date: August 25, 2022
    Inventors: HAN-TING LIN, JIANN-HORNG LIN, HSING-HSIANG WANG, HUAN-JUST LIN, SIN-YI YANG, CHEN-JUNG WANG, KUN-YI LI, MENG-CHIEH WEN, LAN-HSIN CHIANG, LIN-TING LIN
  • Patent number: 11414759
    Abstract: Embodiments of mechanisms for processing a semiconductor wafer are provided. A method for processing a wafer includes providing a wafer process apparatus. The wafer process apparatus includes a chamber and a stage positioned in the chamber for supporting the semiconductor wafer. The method also includes supplying a process gas to the semiconductor wafer via a discharging assembly that is adjacent to the stage. The discharging assembly includes a discharging passage configured without a vertical flow path section.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventor: Su-Horng Lin
  • Patent number: 11328112
    Abstract: In order to expedite testing (such as silicon chip testing), a test pattern that indicates a timing, order, and frequency (e.g., speed) of signals sent during the test may be divided into different portions. Also, a frequency at which each portion of the test pattern is to be run is determined. Each portion is run at a frequency that can be supported by only that portion. As a result, the slowest portion of the test pattern only limits the frequency at which its portion is run, while other portions are run at a faster frequency. This reduces a time taken to run the test pattern in a testing environment.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: May 10, 2022
    Assignee: NVIDIA CORPORATION
    Inventors: Shang-Ju Lee, Li-Wei Ko, Francisco M. Da Silva, Shyh-Horng Lin
  • Publication number: 20220131070
    Abstract: A method for fabricating magnetic tunnel junction (MTJ) pillars is provided. The method includes following operations. A MTJ stack of layers including a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer is provided. A first patterning step is carried out by using a reactive ion etching. In the first patterning step, the second magnetic layer and the tunnel barrier layer are etched to form one or more pillar structures and a protection layer is formed and covers sidewalk of the pillar structures.
    Type: Application
    Filed: October 27, 2020
    Publication date: April 28, 2022
    Inventors: JIANN-HORNG LIN, KUN-YI LI, HAN-TING LIN, HUAN-JUST LIN, CHEN-JUNG WANG, SIN-YI YANG
  • Patent number: 11253581
    Abstract: The present disclosure relates to a composition for preventing and treating Mycoplasma synoviae infection, the composition comprising Tuf, NOX, MS53-0285 or a combination thereof as active ingredients. The composition of the present disclosure is effective in alleviating symptoms caused by Mycoplasma synoviae infection and can be used as an effective tool in preventing or treating poultry diseases.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: February 22, 2022
    Assignee: AGRICULTURAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jiunn-Horng Lin, Ho-Yuan Chou, Jyh-Perng Wang, Zeng-Weng Chen, Weng-Zeng Huang, Hsiu-Hui Wu, Hui-Jie Lin, Sheng-Xiang Huang
  • Publication number: 20220029091
    Abstract: A method for forming a memory device structure is provided. The method includes providing a substrate, a first dielectric layer, a conductive via, a magnetic tunnel junction cell, a first etch stop layer, and a first spacer layer. The substrate has a first region and a second region, the first dielectric layer is over the substrate, the conductive via passes through the first dielectric layer over the first region. The method includes removing the first etch stop layer, which is not covered by the first spacer layer. The method includes removing the first dielectric layer, which is not covered by the first etch stop layer.
    Type: Application
    Filed: July 21, 2020
    Publication date: January 27, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsing-Hsiang WANG, Han-Ting LIN, Yu-Feng YIN, Sin-Yi YANG, Chen-Jung WANG, Yin-Hao WU, Kun-Yi LI, Meng-Chieh WEN, Lin-Ting LIN, Jiann-Horng LIN, An-Shen CHANG, Huan-Just LIN
  • Publication number: 20220002353
    Abstract: The application relates to a dextran affinity tag and use thereof. The present application provides an affinity tag, which is a segment of dextran binding domain, and can purify a target protein by its affinity with the dextran. The affinity tag of the present application has the advantages of more efficient in preparation and purification, and can be widely used in industrial applications that require protein purification processes.
    Type: Application
    Filed: October 29, 2018
    Publication date: January 6, 2022
    Applicant: AGRICULTURAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jiunn-Horng LIN, Jyh-Perng WANG, Zeng-Weng CHEN, Wen-Zheng HUANG, You-Lin ZHUO, Shih-Ling HSUAN
  • Publication number: 20210399207
    Abstract: A magnetic tunnel junction (MTJ) memory cell comprising a connection via structure, a bottom electrode disposed on the connection via structure, a memory material stack disposed on the bottom electrode, and a conductive contact structure disposed on the memory material stack, in which a bottom surface of the conductive contact structure is in direct contact with a memory material layer of the memory material stack.
    Type: Application
    Filed: April 14, 2021
    Publication date: December 23, 2021
    Inventors: Hsing-Hsiang WANG, Yu-Feng YIN, Jiann-Horng LIN, Huan-Just LIN
  • Publication number: 20210380255
    Abstract: An economy class (Y class) private suite includes a continuous seatback and a stowable aisle-side panel. The continuous seatback covers the gaps between seats of a 3-seat or 4-seat PAX and the stowable aisle-side panel slides to close off the PAX from the aisle when desirable. Each seat in the PAX includes an extension element to extend from the anterior surface of the seat cushion and establish a substantially flat surface including the seat cushions and extension elements. A separate padded element may be placed over the substantially flat surface. Each seatback cushion in the PAX is removable and reconfigurable as a reclining support or expanded armrest.
    Type: Application
    Filed: June 4, 2021
    Publication date: December 9, 2021
    Inventors: Horng Lin, Travis Finlay, Glenn A. Johnson