Patents by Inventor Horng Lin

Horng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200135487
    Abstract: In a pattern formation method, a photo resist pattern is formed over a target layer to be patterned. An extension material layer is formed on the photo resist pattern. The target layer is patterned by using at least the extension material layer as an etching mask.
    Type: Application
    Filed: May 31, 2019
    Publication date: April 30, 2020
    Inventors: Yi-Chang LEE, Jiann-Horng LIN, Chih-Hao CHEN, Ying-Hao WU, Wen-Yen CHEN, Shih-Hua TSENG, Shu-Huei SUEN
  • Patent number: 10636667
    Abstract: A method of manufacturing a semiconductor device includes: forming a first mandrel and a second mandrel over a mask layer; depositing a spacer layer over the first mandrel and the second mandrel; forming a line-end cut pattern over the spacer layer between the first mandrel and the second mandrel; depositing a protection layer over the line-end cut pattern; etching the protection layer on the line-end cut pattern; reducing a width of the line-end cut pattern; etching first horizontal portions of the spacer layer with the reduced line-end cut pattern as an etching mask; removing the first mandrel and the second mandrel; and patterning the mask layer using the etched spacer layer and the etched line-end cut pattern as an etch mask.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: April 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jiann-Horng Lin, Chao-Kuei Yeh, Ying-Hao Wu, Tai-Yen Peng, Chih-Hao Chen, Chih-Sheng Tian
  • Publication number: 20200126792
    Abstract: An embodiment is a method of fabricating a semiconductor structure. The method includes utilize uses of a multi-layer structure disposed on a pattern defining layer. In some embodiments, a method of fabricating a semiconductor structure includes forming a first multi-layer structure on a pattern defining layer disposed on a film stack on a substrate, patterning the first multi-layer structure to form an aperture in the first multi-layer structure, forming a first cut opening in the pattern defining layer through the aperture defined by the first multi-layer structure, and forming a second multi-layer structure on the pattern defining layer, a portion of the second multi-layer structure being disposed in the first cut opening.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Inventors: Jiann-Horng Lin, Yi-Chang Lee, Che-Kang Chu, Chih-Hao Chen
  • Publication number: 20200115465
    Abstract: The present disclosure relates to anti-SSEA4 antibodies and bindings fragments thereof comprising specific complementarity determining regions capable of high affinity binding to SSEA4 molecules and SSEA4-associated expressing tumor cells, such as breast cancer, pancreatic cancer, and renal cancer cells. The anti-SSEA4 antibodies and binding fragments induce ADCC or CDC effects in the targeted tumor cells and inhibit and/or reduce the cancer/tumor proliferation. The present disclosure also provides anti-SSEA4 antibodies and binding fragments thereof as a pharmaceutical composition for treating cancer. In addition, the anti-SSEA4 antibodies and binding fragments are useful in the diagnosis of cancers.
    Type: Application
    Filed: December 30, 2019
    Publication date: April 16, 2020
    Inventors: Nan-Horng LIN, Chiu-Chen HUANG, Chien-Yu CHEN, Kuo-Ching CHU, Chi-Huey WONG, Han-Chung WU
  • Publication number: 20200066606
    Abstract: A method includes illuminating a wafer by an X-ray, detecting a spatial domain pattern produced when illuminating the wafer by the X-ray, identifying at least one peak from the detected spatial domain pattern, and analyzing the at least one peak to obtain a morphology of a transistor structure of the wafer.
    Type: Application
    Filed: October 28, 2019
    Publication date: February 27, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Su-Horng LIN, Chi-Ming YANG
  • Publication number: 20200051837
    Abstract: The present disclosure relates to some embodiments of a method for improving processing efficiency of a cluster tool. The method comprises transferring a first lot of wafers from a transfer load lock to a designated storage load lock and transferring a second lot of wafers from the transfer load lock to the designated storage load lock while the first lot of wafers is in the transfer load lock or the designated storage load lock. The designated storage load lock has the same structure as the transfer load lock and respectively has an inner load lock portal at an interface with the first transfer chamber and an outer load lock portal on a sidewall of a front end interface. The inner load lock portal of the designated storage load lock is retained opened during processing. The outer load lock portal of the designated storage load lock is retained closed during processing.
    Type: Application
    Filed: October 18, 2019
    Publication date: February 13, 2020
    Inventors: Su-Horng Lin, Tsung-Hsun Yu, Victor Y. Lu
  • Publication number: 20200023048
    Abstract: Disclosed is a composition for preventing and treating a Mycoplasma hyorhinis infection in swine. The composition uses XylF, DnaK, P72, or a combination thereof as an active pharmaceutical ingredient. Further disclosed are an expression vector and a method for producing the active pharmaceutical ingredient of the composition using a prokaryotic expression system.
    Type: Application
    Filed: August 9, 2016
    Publication date: January 23, 2020
    Inventors: Jiunn-Horng LIN, Zeng-Weng CHEN, Jyh-Perng WANG, Chiung-Wen HSU, Weng-Zeng HUANG, Ming-Wei HSIEH, Tzu-Ting PENG, Shih-Ling HSUAN
  • Patent number: 10538592
    Abstract: The present disclosure relates to anti-SSEA4 antibodies and bindings fragments thereof comprising specific complementarity determining regions capable of high affinity binding to SSEA4 molecules and SSEA4-associated expressing tumor cells, such as breast cancer, pancreatic cancer, and renal cancer cells. The anti-SSEA4 antibodies and binding fragments induce ADCC or CDC effects in the targeted tumor cells and inhibit and/or reduce the cancer/tumor proliferation. The present disclosure also provides anti-SSEA4 antibodies and binding fragments thereof as a pharmaceutical composition for treating cancer. In addition, the anti-SSEA4 antibodies and binding fragments are useful in the diagnosis of cancers.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: January 21, 2020
    Assignee: CHO PHARMA, INC.
    Inventors: Nan-Horng Lin, Chiu-Chen Huang, Chien-Yu Chen, Kuo-Ching Chu, Chi-Huey Wong, Han-Chung Wu
  • Publication number: 20200020532
    Abstract: An embodiment is a method of fabricating a semiconductor structure. The method includes utilize uses of a multi-layer structure disposed on a pattern defining layer. In some embodiments, a method of fabricating a semiconductor structure includes forming a first multi-layer structure on a pattern defining layer disposed on a film stack on a substrate, patterning the first multi-layer structure to form an aperture in the first multi-layer structure, forming a first cut opening in the pattern defining layer through the aperture defined by the first multi-layer structure, and forming a second multi-layer structure on the pattern defining layer, a portion of the second multi-layer structure being disposed in the first cut opening.
    Type: Application
    Filed: July 12, 2018
    Publication date: January 16, 2020
    Inventors: Jiann-Horng Lin, Yi-Chang Lee, Che-Kang Chu, Chih-Hao Chen
  • Patent number: 10515803
    Abstract: An embodiment is a method of fabricating a semiconductor structure. The method includes utilize uses of a multi-layer structure disposed on a pattern defining layer. In some embodiments, a method of fabricating a semiconductor structure includes forming a first multi-layer structure on a pattern defining layer disposed on a film stack on a substrate, patterning the first multi-layer structure to form an aperture in the first multi-layer structure, forming a first cut opening in the pattern defining layer through the aperture defined by the first multi-layer structure, and forming a second multi-layer structure on the pattern defining layer, a portion of the second multi-layer structure being disposed in the first cut opening.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiann-Horng Lin, Yi-Chang Lee, Che-Kang Chu, Chih-Hao Chen
  • Patent number: 10510566
    Abstract: Some embodiments relate to a cluster tool for semiconductor manufacturing. The cluster tool comprises a first transfer chamber having a first transfer robot. The cluster tool further comprises a designated storage chamber and a transfer load lock attached to the first transfer chamber. The cluster tool further comprises a second transfer chamber connected to the first transfer chamber through a pair of via connector chambers, the second transfer chamber having a second transfer robot. The cluster tool further comprises at least three epitaxial deposition chamber attached to the second transfer chamber. The cluster tool further comprises a control unit configured to control the second transfer robot to transfer wafers between the designated storage chamber and the transfer load lock.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Horng Lin, Tsung-Hsun Yu, Victor Y. Lu
  • Publication number: 20190328895
    Abstract: An antibody-drug conjugate (ADC) has a structure represented by Formula (I): a pharmaceutically acceptable salt thereof wherein Ab is an antibody without glycans (i.e., the protein portion an antibody); G1 and G2 are glycan moieties, which may be the same or different; Cn1 and Cn2 are conjugation moieties, which may be the same or different; L1 and L2 are linker moieties, which may be the same or different; D1 and D2; are drug units which may be the same or different; and x and y are independently an integer from 0 to 8, provided that x+y?0.
    Type: Application
    Filed: November 14, 2017
    Publication date: October 31, 2019
    Applicants: CHO PHARMA INC.
    Inventors: Nan-Horng LIN, Charng-Sheng TSAI, Ting-Chun HUNG, Hong-Yang CHUANG
  • Patent number: 10460999
    Abstract: A metrology device includes a light source and an image sensor. The light source is configured for providing an X-ray illuminating a wafer. The image sensor is configured for detecting a spatial domain pattern produced when the X-ray illuminating the wafer.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: October 29, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Su-Horng Lin, Chi-Ming Yang
  • Patent number: 10407673
    Abstract: A mutant of EndoS2 includes one or more mutations in the sequence of a wild-type EndoS2 (SEQ ID NO:1), wherein the one or more mutations are in a peptide region located within residues 133-143, residues 177-182, residues 184-189, residues 221-231, and/or residues 227-237, wherein the mutant of EndoS2 has a low hydrolyzing activity and a high tranglycosylation activity, as compared to those of the wild-type EndoS2. A method for preparing an engineered glycoprotein using the mutant of EndoS2 includes coupling an activated oligosaccharide to a glycoprotein acceptor. The activated oligosaccharide is a glycan oxazoline.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: September 10, 2019
    Assignees: CHO Pharma Inc., Academia Sinica
    Inventors: Nan-Horng Lin, Lin-Ya Huang, Sachin S Shivatare, Li-Tzu Chen, Chi-Huey Wong, Chung-Yi Wu, Ting Cheng
  • Publication number: 20190157094
    Abstract: A method of manufacturing a semiconductor device includes: forming a first mandrel and a second mandrel over a mask layer; depositing a spacer layer over the first mandrel and the second mandrel; forming a line-end cut pattern over the spacer layer between the first mandrel and the second mandrel; depositing a protection layer over the line-end cut pattern; etching the protection layer on the line-end cut pattern; reducing a width of the line-end cut pattern; etching first horizontal portions of the spacer layer with the reduced line-end cut pattern as an etching mask; removing the first mandrel and the second mandrel; and patterning the mask layer using the etched spacer layer and the etched line-end cut pattern as an etch mask.
    Type: Application
    Filed: September 4, 2018
    Publication date: May 23, 2019
    Inventors: JIANN-HORNG LIN, CHAO-KUEI YEH, YING-HAO WU, TAI-YEN PENG, CHIH-HAO CHEN, CHIH-SHENG TIAN
  • Publication number: 20190131131
    Abstract: A method of forming a semiconductor device structure is provided. The method includes successively forming first and second hard mask layers over a trench pattern region of a material layer. The second hard mask layer has a first tapered opening corresponding to a portion of the trench pattern region and a passivation spacer is formed on a sidewall of the first tapered opening to form a second tapered opening therein. The method also includes forming a third tapered opening below the second tapered opening and removing a portion of the passivation spacer in a first etching process. The method also includes forming a vertical opening in the first hard mask layer below the bottom of the third tapered opening in a second etching process. The vertical opening has a width that is substantially equal to a bottom width of the third tapered opening.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 2, 2019
    Inventors: Ying-Hao WU, Chao-Kuei YEH, Tai-Yen PENG, Yun-Yu CHEN, Jiann-Horng LIN, Chih-Hao CHEN
  • Patent number: 10276378
    Abstract: A method of forming a semiconductor device structure is provided. The method includes successively forming first and second hard mask layers over a trench pattern region of a material layer. The second hard mask layer has a first tapered opening corresponding to a portion of the trench pattern region and a passivation spacer is formed on a sidewall of the first tapered opening to form a second tapered opening therein. The method also includes forming a third tapered opening below the second tapered opening and removing a portion of the passivation spacer in a first etching process. The method also includes forming a vertical opening in the first hard mask layer below the bottom of the third tapered opening in a second etching process. The vertical opening has a width that is substantially equal to a bottom width of the third tapered opening.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Hao Wu, Chao-Kuei Yeh, Tai-Yen Peng, Yun-Yu Chen, Jiann-Horng Lin, Chih-Hao Chen
  • Publication number: 20190093113
    Abstract: The present application provides a shuttle vector which can be manipulated in various kinds of host cells, thereby providing a novel tool for the field of genetic engineering. On the other hand, the present application further provides a prokaryotic host cell and a kit comprising said shuttle vector, so as to construct expression vectors which contain the target gene using the shuttle vector, thereby producing proteins in various host cells with one single vector.
    Type: Application
    Filed: September 20, 2018
    Publication date: March 28, 2019
    Applicant: Agricultural Technology Research Institute
    Inventors: Jiunn-Horng LIN, Jyh-Perng WANG, Zeng-Weng CHEN, Wen-Zheng HUANG, Hung-Chih WANG, Shih-Ling HSUAN
  • Publication number: 20190078101
    Abstract: The present invention provides a preparation method for PCV2 capsid protein and a pharmaceutical composition containing said capsid protein. The method of the present invention uses a novel arabinose-induced expression vector and thereby improves the synthesis efficiency of said PCV2 capsid protein. On the other hand, the present pharmaceutical composition combines said capsid protein and other favorable components at a proper ratio so that achieves excellent immune-inducing effects.
    Type: Application
    Filed: December 28, 2015
    Publication date: March 14, 2019
    Applicant: AGRICULTURAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jiunn-Horng LIN, Zeng-Weng CHEN, Jyh-Perng WANG, Tzu-Ting PENG, Huei-Yu LEE, Weng-Zeng HUANG, Shih-Rong WANG, Cheng-Yao YANG
  • Publication number: 20190067022
    Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.
    Type: Application
    Filed: January 15, 2018
    Publication date: February 28, 2019
    Inventors: Jiann-Horng Lin, Cheng-Li Fan, Chih-Hao Chen