Patents by Inventor Hsin-An Hsu

Hsin-An Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230003946
    Abstract: A fiber optic connector includes a ferrule, an insert body, a tail sleeve and two core heads. The ferrule includes an outer frame, and an operating handle extending rearwardly from the outer frame. The outer frame is formed with an inserted opening open along a front-rear direction and two limiting slots open along a left-right direction and spaced apart from each other along the left-right direction. The insert body is detachably inserted into the ferrule and includes two protrusion units protruding away from each other along the left-right direction and respectively movable in the limiting slots.
    Type: Application
    Filed: March 4, 2022
    Publication date: January 5, 2023
    Inventor: Hsien-Hsin HSU
  • Publication number: 20230003945
    Abstract: A fiber optic adaptor includes a main shell body and an outer cover. The main shell body has a first end portion and a second end portion. The first end portion defines a first opening and is formed with two engaging grooves. The outer cover is removably disposed on and covering the first end portion, and has a cover body portion, two locking clips, and an identifier portion. The two locking clips protrudes from the cover and respectively engage the engaging grooves. The identifier portion is disposed on the cover body portion. The locking clips are operable to be removed respectively from the engaging grooves. The cover body portion defines a port outer opening, and a port key portion.
    Type: Application
    Filed: February 23, 2022
    Publication date: January 5, 2023
    Inventors: Yen-Chang LEE, Hsien-Hsin HSU, Jim LIN, Ke Xue NING
  • Patent number: 11543598
    Abstract: An optical fiber connector includes a casing body formed with upper and lower key slots, a polarity adjusting key detachably mounted in a selected one of the key slots and engaging an adaptor, head and tail sleeves disposed respectively on front and rear ends of the casing body, and two core heads disposed between the head sleeve and the casing body. To adjust the polarity of the optical fiber connector, the optical fiber connector is detached from the adaptor and the optical fiber connector is inverted. Then, the polarity adjusting key is operated to disengage from the selected one of the key slots and engage the other one of the key slots to adjust the polarity without removal of head and tail sleeves.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: January 3, 2023
    Assignee: Gloriole Electroptic Technology Corp.
    Inventor: Hsien-Hsin Hsu
  • Patent number: 11545423
    Abstract: The disclosure provides a package structure including a redistribution circuit structure, a first circuit board, a second circuit board, a first insulator, multiple conductive terminals, and a package. The redistribution circuit structure has a first connection surface and a second connection surface opposite to each other. The first circuit board and the second circuit board are disposed on the first connection surface and are connected electrically to the redistribution circuit structure. The first insulator is disposed on the first connection surface and covers the first circuit board and the second circuit board. The conductive terminals are connected electrically to and disposed on the first circuit board or the second circuit board. The package is disposed on the second connection surface and is connected electrically to the redistribution circuit structure. A manufacturing method of a package structure is also provided.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: January 3, 2023
    Assignee: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Nan-Chun Lin, Hung-Hsin Hsu
  • Patent number: 11545424
    Abstract: A package structure including a redistribution circuit structure, an insulator, a plurality of conductive connection pieces, a first chip, a second chip, an encapsulant, a third chip, and a plurality of conductive terminals is provided. The redistribution circuit structure has first and second connection surfaces opposite to each other. The insulator is embedded in and penetrates the redistribution circuit structure. The conductive connection pieces penetrate the insulator. The first and second chips are disposed on the first connection surface. The encapsulant is disposed on the redistribution circuit structure and at least laterally covers the first and second chips. The third chip is disposed on the second connection surface and electrically connected to the first and second chips through the conductive connection pieces. The conductive terminals are disposed on the second connection surface and electrically connected to the first chip or the second chip through the redistribution circuit structure.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: January 3, 2023
    Assignee: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Nan-Chun Lin, Hung-Hsin Hsu
  • Patent number: 11538917
    Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer and a titanium aluminide layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and a thickness of the titanium aluminide layer ranges from twice a thickness of the titanium nitride barrier layer to three times the thickness of the titanium nitride barrier layer.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: December 27, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Hsin Hsu, Huan-Chi Ma, Chien-Wen Yu, Shih-Min Chou, Nien-Ting Ho, Ti-Bin Chen
  • Publication number: 20220403328
    Abstract: A composite material film for expanding circulating tumor cells ex vivo and a preparation method thereof, a kit and a method for expanding circulating tumor cells ex vivo, a method for detecting an effect of a drug, and a cryopreservation solution are provided. The preparation method includes: mixing one or more kinds of particles and a solvent to form a mixed liquid, in which the particles are selected from the group consisting of metal particles, metal oxide particles, silicon oxide particles and combinations thereof; placing the mixed liquid on a substrate to form a particle layer; adding a medium material to the particle layer, in which the medium material is selected from the group consisting of styrene and its derivatives, polyester monomers, silicon oxide compounds and combinations thereof; and polymerizing the medium material to form a medium layer to fix the particle layer on the substrate.
    Type: Application
    Filed: November 5, 2020
    Publication date: December 22, 2022
    Inventors: Po-Han Chen, Wei-Hsin Hsu, Shih-Pei Wu
  • Patent number: 11532575
    Abstract: An integrated antenna package structure including a chip, a circuit layer, an encapsulant, a coupling end, an insulating layer, a conductive connector, a dielectric substrate, and an antenna is provided. The circuit layer is electrically connected to the chip. The encapsulant is disposed on the circuit layer and covers the chip. The coupling end is disposed on the encapsulant. The insulating layer covers the coupling end. The insulating layer is not externally exposed. The conductive connector penetrates the encapsulant. The coupling end is electrically connected to the circuit layer by the conductive connection. The dielectric substrate is disposed on the encapsulant and covers the coupling end. The antenna is disposed on the dielectric substrate. A manufacturing method of an integrated antenna package structure is also provided.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: December 20, 2022
    Assignee: Powertech Technology Inc.
    Inventors: Han-Wen Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien, Nan-Chun Lin
  • Publication number: 20220391307
    Abstract: A device for building a test file comprises a receiving module, for receiving a first request of a first user and for analyzing the first request, and for notifying an analysis result of the first request to the first user; a building module, coupled to the receiving module, for building the test file according to the first request of a task queue; and a transmitting module, coupled to the building module, for notifying a building result of the test file to the first user.
    Type: Application
    Filed: August 2, 2021
    Publication date: December 8, 2022
    Applicants: Inventec (Pudong) Technology Corp., Inventec Corporation
    Inventors: Che-Sheng Cheng, Yen-Chen Chuang, Kuo-Hsin Hsu
  • Patent number: 11522000
    Abstract: A semiconductor package structure including a sensor die, a substrate, a light blocking layer, a circuit layer, a dam structure and an underfill is provided. The sensor die has a sensing surface. The sensing surface includes an image sensing area and a plurality of conductive bumps. The substrate is disposed on the sensing surface. The light blocking layer is located between the substrate and the sensor die. The circuit layer is disposed on the light blocking layer. The sensor die is electrically connected to the circuit layer by the conductive bumps. The dam structure is disposed on the substrate and surrounds the image sensing area. Opposite ends of the dam structure directly contact the sensor die and the light blocking layer. The underfill is disposed between the dam structure and the conductive bumps.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: December 6, 2022
    Assignee: Powertech Technology Inc.
    Inventors: Hung-Hsin Hsu, Wen-Hsiung Chang
  • Patent number: 11518662
    Abstract: A lid opening component, a lid opening device, and a suction system are disclosed. The suction system includes the lid opening device and a suction assembly, wherein the lid opening device includes a positioning assembly and a lid opening assembly having the lid opening components, and the lid opening component includes a needle holder, a plurality of unpowered needles, and a drive part. The suction system identifies the locations of a container and its lids through the positioning assembly of the lid opening device, opens the container's lids by fitting the unpowered needles of the lid opening components in with the surfaces of the container's lids and rotating the lid opening components of the lid opening assembly, and by moving the suction assembly to the openings of the container, draws out the content in the container through the suction assembly.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: December 6, 2022
    Assignee: ASIA IC MIC-PROCESS, INC.
    Inventors: Hung-Hsin Hsu, Yan-Lan Chiou
  • Publication number: 20220384603
    Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer and a titanium aluminide layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and a thickness of the titanium aluminide layer ranges from twice a thickness of the titanium nitride barrier layer to three times the thickness of the titanium nitride barrier layer.
    Type: Application
    Filed: June 22, 2021
    Publication date: December 1, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Hsin Hsu, Huan-Chi Ma, Chien-Wen Yu, Shih-Min Chou, Nien-Ting Ho, Ti-Bin Chen
  • Publication number: 20220366379
    Abstract: An intelligent monitoring system for waste disposal and the method thereof are provided, which include a plurality of operational devices and stages. First, a transportation stage is performed to loading a transport vehicle with a waste so as to transport the waste to a disposal station for further treatment. A camera and a sensor for detecting abnormal conditions are installed any one of the operational devices or installed in the operational path of any one of the operational devices. The camera records the videos of the operational stages, captures the images from the videos and recognizes the images in order to determine whether the abnormal conditions occur in any one of the operational stages. Alternatively, the camera is triggered to capture the images and recognize the images after the abnormal conditions are detected by the sensor in order to determine whether the abnormal conditions actually occur.
    Type: Application
    Filed: June 12, 2021
    Publication date: November 17, 2022
    Inventors: YUNG-FA YANG, TSUNG-TIEN CHEN, SHAO-HSIN HSU, BO-WEI CHEN, CHIA-CHING CHEN, MING-HUA TANG
  • Patent number: 11480869
    Abstract: A photomask includes a substrate, a multilayer stack disposed over the substrate and configured to reflect a radiation, a capping layer over the multilayer stack, and an anti-reflective layer over the capping layer. The anti-reflective layer comprises a first pattern, wherein the first pattern exposes the capping layer and is configured as a printable feature. The photomask also includes an absorber spaced apart from the printable feature from a top-view perspective.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: October 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chien-Hung Lai, Hao-Ming Chang, Chia-Shih Lin, Hsuan-Wen Wang, Yu-Hsin Hsu, Chih-Tsung Shih, Yu-Hsun Wu
  • Publication number: 20220328422
    Abstract: A fan-out semiconductor package includes: a redistribution structure; a functional chip coupled to the redistribution structure; an isolation structure disposed on the redistribution structure and including a body formed with through-holes; a shielding structure disposed on the isolation structure and the redistribution structure; a first conductive pattern structure disposed on the isolation structure and extending through the through-holes of the isolation structure; an encapsulating structure disposed on the isolation structure, the shielding structure and the first conductive pattern structure; and a second conductive pattern structure disposed on the encapsulating structure. A method for manufacturing the fan-out semiconductor package is also disclosed.
    Type: Application
    Filed: November 12, 2021
    Publication date: October 13, 2022
    Applicant: Powertech Technology Inc.
    Inventors: Shang-Yu CHANG CHIEN, Nan-Chun LIN, Hung-Hsin HSU
  • Publication number: 20220320052
    Abstract: A package structure, including a redistribution circuit layer, a first die, a dielectric body, a first connection circuit, a patterned insulating layer, a second die and a third die, is provided. The first die is disposed on the redistribution circuit layer and is electrically connected to the redistribution circuit layer. The dielaectric body is disposed on the redistribution circuit layer and covers the first die. The first connection circuit is disposed on the dielectric body and is electrically connected to the redistribution circuit layer. The patterned insulating layer covers the first connection circuit. A portion of the patterned insulating layer is embedded in the dielectric body. The second die is disposed on the dielectric body and is electrically connected to the first connection circuit. The third die is disposed on the redistribution circuit layer, is opposite to the first die, and is electrically connected to the redistribution circuit layer.
    Type: Application
    Filed: June 9, 2021
    Publication date: October 6, 2022
    Applicant: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Nan-Chun Lin, Hung-Hsin Hsu
  • Patent number: 11456243
    Abstract: A semiconductor package structure, including a circuit substrate, at least two chips, an encapsulant, and a redistribution layer, is provided. The circuit substrate has a first surface and a second surface opposite to the first surface. The at least two chips are disposed on the first surface. Each of the at least two chips has an active surface facing the circuit substrate and includes multiple first conductive connectors and multiple second conductive connectors disposed on the active surface. A pitch of the first conductive connectors is less than a pitch of the second conductive connectors. The encapsulant encapsulates the at least two chips. The redistribution layer is located on the second surface. The first conductive connectors are electrically connected to the redistribution layer by the circuit substrate. The second conductive connectors are electrically connected to the circuit substrate. A manufacturing method of a semiconductor package structure is also provided.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: September 27, 2022
    Assignee: Powertech Technology Inc.
    Inventors: Nan-Chun Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien
  • Publication number: 20220302061
    Abstract: A semiconductor package and fabricating method thereof are disclosed. The semiconductor package has a chip, a plurality of first and second bumps, an encapsulation, a redistribution. The chip has a plurality of pads and an active area and the active surface has a first area and a second area surrounding the first area. The pads are formed on a first area of the active surface. Each first bump is formed on the corresponding pad. The second bumps are formed on the second area and each second bump has a first layer and a second layer with different widths. The encapsulation encapsulates the chip and the first and second bumps and is ground to expose the first and second bumps therefrom. During grinding, all of the first bumps are completely exposed by determining a width of an exposed surface of the second bump to electrically connect to the redistribution is increased.
    Type: Application
    Filed: August 3, 2021
    Publication date: September 22, 2022
    Applicant: Powertech Technology Inc.
    Inventors: Shang-Yu CHANG-CHIEN, Hung-Hsin HSU, Nan-Chun LIN
  • Publication number: 20220293679
    Abstract: A semiconductor memory device includes a substrate, a dielectric layer on the substrate, and a contact plug in the dielectric layer. An upper portion of the contact plug protrudes from a top surface of the dielectric layer. The upper portion of the contact plug acts as a first electrode. A buffer layer is disposed on the dielectric layer and beside the upper portion of the contact plug. A resistive-switching layer is disposed beside the buffer layer. A second electrode is disposed beside the resistive-switching layer.
    Type: Application
    Filed: April 7, 2021
    Publication date: September 15, 2022
    Inventors: Wen-Hsin Hsu, Ko-Chi Chen, Tzu-Yun Chang, Chung-Tse Chen
  • Publication number: 20220236494
    Abstract: A fiber optic adapter includes a shell body defining an inner space, a dividing wall dividing the inner space into two receptacles, an installation seat, and a securing seat. The installation seat and the securing seat are respectively located in the receptacles. The securing seat includes a plurality of base walls connected in pairs, a plurality of pairs of clamping walls, and a plurality of clenching walls. Each base wall cooperates with a respective pair of the clamping walls and a respective clenching wall to form a ring-shaped structure, with each adjacent two of the base wall, the pair of clamping walls and the clenching wall defining a gap therebetween.
    Type: Application
    Filed: January 5, 2022
    Publication date: July 28, 2022
    Inventor: Hsien-Hsin HSU