Patents by Inventor Hussein I. Hanafi
Hussein I. Hanafi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8872324Abstract: Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.Type: GrantFiled: May 14, 2014Date of Patent: October 28, 2014Assignee: Micron Technology, Inc.Inventors: Paul A. Farrar, Hussein I Hanafi
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Publication number: 20140247638Abstract: Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.Type: ApplicationFiled: May 14, 2014Publication date: September 4, 2014Applicant: Micron Technology, Inc.Inventors: Paul A. Farrar, Hussein I. Hanafi
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Patent number: 8729691Abstract: Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.Type: GrantFiled: July 16, 2013Date of Patent: May 20, 2014Assignee: Micron Technology, Inc.Inventors: Paul D. Farrar, Hussein I Hanafi
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Publication number: 20130299999Abstract: Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.Type: ApplicationFiled: July 16, 2013Publication date: November 14, 2013Inventors: Paul A. Farrar, Hussein I. Hanafi
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Patent number: 8498171Abstract: Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.Type: GrantFiled: August 6, 2012Date of Patent: July 30, 2013Assignee: Micron Technology, Inc.Inventors: Paul A. Farrar, Hussein I Hanafi
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Patent number: 8367505Abstract: Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate, and a third gate, e.g., a control gate, a back gate, and a floating gate, as a memory in logic cell. The method includes programming the floating gate to a first state to cause the memory in logic cell to operate as a first logic gate type. The method further includes programming the floating gate to a second state to cause the memory in logic cell to operate as a second logic gate type.Type: GrantFiled: November 10, 2009Date of Patent: February 5, 2013Assignee: Micron Technology, Inc.Inventors: Hussein I. Hanafi, Leonard Forbes, Alan R. Reinberg
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Patent number: 8324676Abstract: Methods, devices, and systems for a memory cell are provided. One embodiment includes a memory cell with a storage node separated from a body region by a first dielectric, wherein the body region includes a channel separating a source and a drain region, and wherein a length of the storage node is less than a length of the channel. The embodiment further includes a memory cell with a gate separated from the storage node by a second dielectric, wherein a length of the gate is greater than a length of the storage node.Type: GrantFiled: December 16, 2009Date of Patent: December 4, 2012Assignee: Micron Technology, Inc.Inventor: Hussein I. Hanafi
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Publication number: 20120302006Abstract: Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.Type: ApplicationFiled: August 6, 2012Publication date: November 29, 2012Inventors: Paul A. Farrar, Hussein I. Hanafi
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Patent number: 8242555Abstract: Methods, devices and systems for a FinFET are provided. One method embodiment includes forming a FinFET by forming a relaxed silicon germanium (Si1-XGeX) body region for a fully depleted Fin field effect transistor (FinFET) having a body thickness of at least 10 nanometers (nm) for a process design rule of less than 25 nm. The method also includes forming a source and a drain on opposing ends of the body region, wherein the source and the drain are formed with halo ion implantation and forming a gate opposing the body region and separated therefrom by a gate dielectric.Type: GrantFiled: February 5, 2010Date of Patent: August 14, 2012Assignee: Micron Technology, Inc.Inventor: Hussein I. Hanafi
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Patent number: 8237254Abstract: Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.Type: GrantFiled: May 20, 2011Date of Patent: August 7, 2012Assignee: Micron Technology, Inc.Inventors: Paul A. Farrar, Hussein I Hanafi
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Publication number: 20110222328Abstract: Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.Type: ApplicationFiled: May 20, 2011Publication date: September 15, 2011Inventors: Paul A. Farrar, Hussein I. Hanafi
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Patent number: 7955917Abstract: A method for fabricating a gallium arsenide MOSFET device is presented. A dummy gate is formed over a gallium arsenide substrate. Source-drain extensions are implanted into the substrate adjacent the dummy gate. Dummy spacers are formed along dummy gate sidewalls and over a portion of the source-drain extensions. Source-drain regions are implanted. Insulating spacers are formed on dummy oxide spacer sidewalls. A conductive layer is formed over the source-drain regions. The conductive layer is annealed to form contacts to the source-drain regions. The dummy gate and the dummy oxide spacers are removed to form a gate opening. A passivation layer is in-situ deposited in the gate opening. The surface of the passivation layer is oxidized to create an oxide layer. A dielectric layer is ex-situ deposited over the oxide layer. A gate metal is deposited over the dielectric layer to form a gate stack in the gate opening.Type: GrantFiled: September 18, 2008Date of Patent: June 7, 2011Assignee: Micron Technology, Inc.Inventor: Hussein I. Hanafi
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Patent number: 7952913Abstract: One method for operating an SRAM cell includes applying a potential to a back gate of a pair of cross coupled p-type pull up transistors in the SRAM during a write operation. The method includes applying a ground to the back gate of the pair of cross coupled p-type pull up transistors during a read operation. The charge stored on a pair of cross coupled storage nodes of the SRAM is coupled to a front gate and a back gate of a pair of cross coupled n-type pull down transistors in the SRAM during the write operation and during a read operation.Type: GrantFiled: April 1, 2010Date of Patent: May 31, 2011Assignee: Micron Technology, Inc.Inventor: Hussein I. Hanafi
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Patent number: 7952184Abstract: Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.Type: GrantFiled: August 31, 2006Date of Patent: May 31, 2011Assignee: Micron Technology, Inc.Inventors: Paul A. Farrar, Hussein I Hanafi
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Patent number: 7934181Abstract: The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage (Vdd?) is applied to the word line of a selected SRAM cell, while such a boosted word line voltage (Vdd?) is sufficiently higher than the power supply voltage (Vdd) of the SRAM cell so as to improve the cell stability to a desired level. Specifically, a specific boosted word line voltage is predetermined for each SRAM cell based on the specific cell configuration, by using a circuit simulation program, such as the BERKELEY-SPICE simulation program. A boost voltage generator is then used to apply the predetermined boosted word line voltage to the selected SRAM cell.Type: GrantFiled: May 30, 2008Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Hussein I. Hanafi, Richard Q. Williams
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Patent number: 7928503Abstract: Some embodiments include methods of forming memory cells. Dopant is implanted into a semiconductor substrate to form a pair of source/drain regions that are spaced from one another by a channel region. The dopant is annealed within the source/drain regions, and then a plurality of charge trapping units are formed over the channel region. Dielectric material is then formed over the charge trapping units, and control gate material is formed over the dielectric material. Some embodiments include memory cells that contain a plurality of nanosized islands of charge trapping material over a channel region, with adjacent islands being spaced from one another by gaps. The memory cells can further include dielectric material over and between the nanosized islands, with the dielectric material forming a container shape having an upwardly opening trough therein. The memory cells can further include control gate material within the trough.Type: GrantFiled: May 21, 2010Date of Patent: April 19, 2011Assignee: Micron Technology, Inc.Inventor: Hussein I. Hanafi
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Patent number: 7875529Abstract: Methods, devices, modules, and systems providing semiconductor devices in a stacked wafer system are described herein. One embodiment includes a first wafer for NMOS transistors in a CMOS architecture and a second wafer for PMOS transistors in the CMOS architecture, with the first wafer being bonded and electrically coupled to the second wafer to form at least one CMOS device. Another embodiment includes a number of DRAM capacitors formed on a first wafer and support circuitry associated with the DRAM capacitors formed on a second wafer, with the first wafer being bonded and electrically coupled to the second wafer to form a number of DRAM cells. Another embodiment includes a first wafer having a number of vertical transistors coupled to a data line and a second wafer having amplifier circuitry associated with the number of vertical transistors, with the first wafer being bonded and electrically coupled to the second wafer.Type: GrantFiled: October 5, 2007Date of Patent: January 25, 2011Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Paul A. Farrar, Arup Bhattacharyya, Hussein I. Hanafi, Warren M. Farnworth
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Publication number: 20100224930Abstract: Some embodiments include methods of forming memory cells. Dopant is implanted into a semiconductor substrate to form a pair of source/drain regions that are spaced from one another by a channel region. The dopant is annealed within the source/drain regions, and then a plurality of charge trapping units are formed over the channel region. Dielectric material is then formed over the charge trapping units, and control gate material is formed over the dielectric material. Some embodiments include memory cells that contain a plurality of nanosized islands of charge trapping material over a channel region, with adjacent islands being spaced from one another by gaps. The memory cells can further include dielectric material over and between the nanosized islands, with the dielectric material forming a container shape having an upwardly opening trough therein. The memory cells can further include control gate material within the trough.Type: ApplicationFiled: May 21, 2010Publication date: September 9, 2010Applicant: MICRON TECHNOLOGY, INC.Inventor: Hussein I. Hanafi
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Patent number: 7791941Abstract: Methods, devices and systems for non-volatile static random access memory (SRAM) are provided. One method embodiment for operating an SRAM includes transferring data from a pair of static storage nodes of the SRAM to a pair of non-volatile storage nodes when the SRAM is placed in a standby mode. The method further includes transferring data from the pair of non-volatile storage nodes to the pair of static storage nodes when the SRAM exits the standby mode.Type: GrantFiled: October 26, 2007Date of Patent: September 7, 2010Assignee: Micron Technology, Inc.Inventor: Hussein I. Hanafi
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Publication number: 20100188889Abstract: Methods, devices and systems for a back gated static random access memory (SRAM) cell are provided. One method embodiment for operating an SRAM cell includes applying a potential to a back gate of a pair of cross coupled p-type pull up transistors in the SRAM during a write operation. The method includes applying a ground to the back gate of the pair of cross coupled p-type pull up transistors during a read operation. The charge stored on a pair of cross coupled storage nodes of the SRAM is coupled to a front gate and a back gate of a pair of cross coupled n-type pull down transistors in the SRAM during the write operation and during a read operation.Type: ApplicationFiled: April 1, 2010Publication date: July 29, 2010Applicant: MICRON TECHNOLOGY, INC.Inventor: Hussein I. Hanafi