Abstract: Metal oxide semiconductor field effect transistor (MOSFET) comprising a drain region and source region which enclose a channel region. A thin gate oxide is situated on the channel region and a gate conductor with vertical side walls is located on this gate oxide. The interfaces between the source region and channel region and the drain region and channel region are abrupt.

Abstract: Disclosed is a method of protecting semiconductor areas while exposing a gate for processing on a semiconductor surface, the method comprising depositing a planarizing high density plasma layer of a silicon compound, selected from the group silicon oxide and silicon nitride, in a manner effective in leaving an upper surface of said gate exposed. Also disclosed is a method of processing short gates while protecting long gates on a semiconductor surface, the method comprising depositing a planarizing layer of a silicon compound, selected from the group silicon nitride and silicon oxide, up to substantially the same height as said gates, and processing said semiconductor surface.

Abstract: A transistor has a gate with a variable work function and a gate oxide layer with variable thickness. The gate oxide layer has an area of reduced thickness at its center, and the gate is made from central and peripheral portions. The central portion is formed over the central (thinner) portion of the gate oxide layer, and the peripheral portions are formed over the thicker areas of the gate oxide layer. The gate, gate oxide layer, and two source/drain regions may be formed in a damascene trench for improved performance, and lightly doped drain (LDD) regions preferably extend from the source/drain regions in overlapping relationship with the peripheral portions of the gate. Additionally, a method for making an asymmetrical transistor is presented, which involves applying a gate oxide layer on a semiconductor layer in contact with a sidewall structure. A first spacer made of a gate material is formed on the structure and gate oxide layer.

Abstract: A technique for forming a sub-0.05 &mgr;m channel length double-gated/double channel MOSFET structure having excellent short-channel characteristics as well as the double-gated/double channel MOSFET structure itself is provided herein. The inventive technique utilizes a damascene process for the fabrication of a MOSFET device with double-gate/double channel structure. The gates are present on opposite sides of a silicon film having a vertical thickness of about 80 nm or less which is present in the gate region. The silicon film serves as the vertical channel regions of the structure and connects diffusion regions that are abutting the gate region to each other. In the inventive device, the current is double that of a conventional planar MOSFET with the same physical width due to its dual channel feature.

Abstract: A process and etchant gas composition for anisotropically etching a trench in a silicon nitride layer of a multilayer structure. The etchant gas composition has an etchant gas including a polymerizing agent, a hydrogen source, an oxidant, and a noble gas diluent. The oxidant preferably includes a carbon-containing oxidant component and an oxidant-noble gas component. The fluorocarbon gas is selected from CF4, C2F6, and C3F8; the hydrogen source is selected from CHF3, CH2F2, CH3F, and H2; the oxidant is selected from CO, CO2, and O2; and the noble gas diluent is selected from He, Ar, and Ne. The constituents are added in amounts to achieve an etchant gas having a high nitride selectivity to silicon oxide and photoresist. A power source, such as an RF power source, is applied to the structure to control the directionality of the high density plasma formed by exciting the etchant gas.

Abstract: A method of fabricating MOSFET devices in which the gate polysilicon is not consumed during damascene etch back, comprising: (a) forming a gate stack on a surface of a silicon-containing substrate, said gate stack having at least a pad oxide layer formed on said surface of said silicon-containing substrate and a nitride layer formed on said pad oxide layer; (b) forming a trough in said gate stack stopping on said pad oxide layer exposing a portion of said pad oxide layer, said trough having vertical sidewalls; (c) forming a conformal silicon layer on said gate stack and in said trough, including said vertical sidewalls and said exposed pad oxide layer; (d) removing the conformal silicon layer from said gate stack and said exposed pad oxide layer whereby silicon remains on the vertical sidewalls of said trough; (e) removing the exposed pad oxide from said trough exposing a portion of the silicon-containing substrate; (f) oxidizing the silicon on said vertical sidewalls of the trough and in said exposed silicon

Abstract: Metal oxide semiconductor field effect transistor (MOSFET) including a drain region and a source region adjacent to a channel region. A gate oxide is situated on the channel region and a gate conductor with vertical side walls is placed on the gate oxide. The MOSFET further includes a threshold adjust implant region and/or punch through implant region being aligned with respect to the gate conductor and limited to an area underneath the gate conductor.

Abstract: A method for the formation of field effect transistors (FETs), and more particularly metal oxide field effect transistors (MOSFETs), comprising the steps of: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack; defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; depositing a side wall layer; removing the side wall layer from horizontal surfaces of the dielectric stack and gate hole such that side wall spacers remain which reduce the lateral size of the gate hole; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering the portions of the semiconductor structure surrounding the gate hole; removing at least part of the dielectric stack; and removing the side wall spacers.

Abstract: Decoupled plasma etching process used to make a protruding structure having vertical or near vertical sidewalls. The decoupled plasma etching process comprises the following steps:forming a mask on top of a semiconductor substrate defining the lateral size of the protruding structures to be formed in said substrate,feeding HCl, Cl.sub.2 and N.sub.2 into a plasma chamber to provide an ion plasma when applying source power,causing said ions to diffuse towards the substrate by applying a bias power such that the portions of said substrate not being covered by said mask are etched away, wherein the dosage of HCl, Cl.sub.2 and N.sub.2 is chosen such that newly formed portions of the sidewall surfaces are passivated by by-product of Si, Cl, and N.sub.2 and thus become protected from further being etched. The bias power is less than 70 Watts to ensure that the etching process is predominantly chemical.

Abstract: An off-chip driver circuit which includes a complementary pair of field effect transistor source followers connected in a non-inverting series circuit arrangement. The driver circuit includes an n-channel device to pull the output up to the positive supply less the threshold drop across the device and a p-channel device to pull the output down for the opposite transition to within a threshold voltage drop above ground of the p-channel device. The driver circuit includes means for eliminating body effect by connecting the n(p)-well of the p(n) channel transistor to the output node. The driver circuit provides a reduced swing low noise output which reduces the collapse of the power supply. The driver circuit provides an appropriate impedance match to the output transmission line, so that the output transmission line can be terminated to eliminate reflections.