Patents by Inventor Hussein I. Hanafi
Hussein I. Hanafi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7089515Abstract: A method for compensating the threshold voltage roll-off using transistors containing back-gates or body nodes is provided. The method includes designing a semiconductor system or chip having a plurality of transistors with a channel length of Lnom. For the present invention, it is assumed that the channel length of these transistors at the completion of chip manufacturing is Lmax. This enables one to set the off-current to the maximum value of I-offmax which is done by setting the threshold voltage value to Vtmin. The Vtmin for these transistors is obtained during processing by using the proper implant dose. After manufacturing, the transistors are then tested to determine the off-current thereof. Some transistors within the system or chip will have an off-current value that meets a current specification. For those transistor devices, no further compensation is required. For other transistors within the system or chip, the off-current is not within the predetermined specification.Type: GrantFiled: March 9, 2004Date of Patent: August 8, 2006Assignee: International Business Machines CorporationInventors: Hussein I. Hanafi, Robert H. Dennard, Wilfried E. Haensch
-
Patent number: 7078773Abstract: A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.Type: GrantFiled: December 23, 2002Date of Patent: July 18, 2006Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Hussein I. Hanafi, Paul M. Solomon
-
Patent number: 7056773Abstract: A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced by implantation, either enhances or retards dielectric formation.Type: GrantFiled: April 28, 2004Date of Patent: June 6, 2006Assignee: International Business Machines CorporationInventors: Andres Bryant, Omer H. Dokumaci, Hussein I. Hanafi, Edward J. Nowak
-
Patent number: 7018873Abstract: provides SOI CMOS technology whereby a polysilicon back-gate is used to control the threshold voltage of the front-gate device, and the nMOS and pMOS back-gates are switched independently of each other and the front gates. Specifically, the present invention provides a method of fabricating a back-gated fully depleted CMOS device in which the device's back-gate is self-aligned to the device's front-gate as well as the source/drain extension. Such a structure minimizes the capacitance, while enhancing the device and circuit performance. The back-gated fully depleted CMOS device of the present invention is fabricated using existing SIMOX (separation by ion implantation of oxygen) or bonded SOI wafer bonding and thinning, polySi etching, low-pressure chemical vapor deposition and chemical-mechanical polishing.Type: GrantFiled: August 13, 2003Date of Patent: March 28, 2006Assignee: International Business Machines CorporationInventors: Robert H. Dennard, Wilfried E. Haensch, Hussein I. Hanafi
-
Patent number: 6916694Abstract: The present invention provides a method using a damascene-gate process to improve the transport properties of FETs through strain Si. Changes in mobility and FET characteristics are deliberately made in a Si or silicon-on-insulator (SOI) structure through the introduction of local strain in the channel region, without introducing strain in the device source and drain regions. The method has the advantage of not straining the source and drain regions resulting in very low leakage junctions and also it does not require any special substrate preparation like the case of a strained Si/relaxed SiGe system. Moreover, the method is compatible with existing mainstream CMOS processing. The present invention also provides a CMOS device that has a localized strained Si channel that is formed using the method of the present invention.Type: GrantFiled: August 28, 2003Date of Patent: July 12, 2005Assignee: International Business Machines CorporationInventors: Hussein I. Hanafi, David J. Frank, Kevin K. Chan
-
Patent number: 6841831Abstract: A sub-0.05 ?m channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 ?m channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.Type: GrantFiled: June 13, 2003Date of Patent: January 11, 2005Assignee: International Business Machines CorporationInventors: Hussein I. Hanafi, Diane C. Boyd, Kevin K. Chan, Wesley Natzle, Leathen Shi
-
Patent number: 6835614Abstract: A technique for forming a sub-0.05 &mgr;m channel length double-gated/double channel MOSFET structure having excellent short-channel characteristics as well as the double-gated/double channel MOSFET structure itself is provided herein. The inventive technique utilizes a damascene process for the fabrication of a MOSFET device with double-gate/double channel structure. The gates are present on opposite sides of a silicon film having a vertical thickness of about 80 nm or less which is present in the gate region. The silicon film serves as the vertical channel regions of the structure and connects diffusion regions that are abutting the gate region to each other. In the inventive device, the current is double that of a conventional planar MOSFET with the same physical width due to its dual channel feature.Type: GrantFiled: June 30, 2003Date of Patent: December 28, 2004Assignee: International Business Machines CorporationInventors: Hussein I. Hanafi, Jeffrey J. Brown, Wesley C. Natzle
-
Patent number: 6835633Abstract: A method of fabricating a SOI wafer having a gate-quality, thin buried oxide region is provided. The wafer is fabricating by forming a substantially uniform thermal oxide on a surface of a Si-containing layer of a SOI substrate which includes a buried oxide region positioned between the Si-containing layer and a Si-containing substrate layer. Next, a cleaning process is employed to form a hydrophilic surface on the thermal oxide. A carrier wafer having a hydrophilic surface is provided and positioned near the substrate such that the hydrophilic surfaces adjoin each other. Room temperature bonding is then employed to bond the carrier wafer to the substrate. An annealing step is performed and thereafter, the Si-containing substrate of the silicon-on-insulator substrate and the buried oxide region are selectively removed to expose the Si-containing layer.Type: GrantFiled: July 24, 2002Date of Patent: December 28, 2004Assignee: International Business Machines CorporationInventors: Diane C. Boyd, Hussein I. Hanafi, Erin C. Jones, Dominic J. Schepis, Leathen Shi
-
Patent number: 6815296Abstract: A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided. The SOI MOSFET device includes a polysilicon back-gate which controls the threshold voltage of a polysilicon-containing front-gate. The back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.Type: GrantFiled: September 11, 2003Date of Patent: November 9, 2004Assignee: International Business Machines CorporationInventors: Robert H. Dennard, Wilfried E. Haensch, Hussein I. Hanafi
-
Patent number: 6812527Abstract: A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided in which an implanted back-gate is formed into a Si-containing layer of an SOI wafer. The implanted back-gate thus formed is capable of controlling the threshold voltage of a polysilicon-containing front-gate which is formed over a portion of the implanted back-gate region. The implanted back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.Type: GrantFiled: September 5, 2002Date of Patent: November 2, 2004Assignee: International Business Machines CorporationInventors: Robert H. Dennard, Wilfried E. Haensch, Hussein I. Hanafi
-
Publication number: 20040119115Abstract: A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.Type: ApplicationFiled: December 23, 2002Publication date: June 24, 2004Inventors: Kevin K. Chan, Hussein I. Hanafi, Paul M. Solomon
-
Publication number: 20040092067Abstract: A technique for forming a sub-0.05 &mgr;m channel length double-gated/double channel MOSFET structure having excellent short-channel characteristics as well as the double-gated/double channel MOSFET structure itself is provided herein. The inventive technique utilizes a damascene process for the fabrication of a MOSFET device with double-gate/double channel structure. The gates are present on opposite sides of a silicon film having a vertical thickness of about 80 nm or less which is present in the gate region. The silicon film serves as the vertical channel regions of the structure and connects diffusion regions that are abutting the gate region to each other. In the inventive device, the current is double that of a conventional planar MOSFET with the same physical width due to its dual channel feature.Type: ApplicationFiled: June 30, 2003Publication date: May 13, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hussein I. Hanafi, Jeffrey J. Brown, Wesley C. Natzle
-
Publication number: 20040046207Abstract: A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided in which an implanted back-gate is formed into a Si-containing layer of an SOI wafer. The implanted back-gate thus formed is capable of controlling the threshold voltage of a polysilicon-containing front-gate which is formed over a portion of the implanted back-gate region. The implanted back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.Type: ApplicationFiled: September 5, 2002Publication date: March 11, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert H. Dennard, Wilfried E. Haensch, Hussein I. Hanafi
-
Publication number: 20040018699Abstract: A method of fabricating a SOI wafer having a gate-quality, thin buried oxide region is provided. The wafer is fabricating by forming a substantially uniform thermal oxide on a surface of a Si-containing layer of a SOI substrate which includes a buried oxide region positioned between the Si-containing layer and a Si-containing substrate layer. Next, a cleaning process is employed to form a hydrophilic surface on the thermal oxide. A carrier wafer having a hydrophilic surface is provided and positioned near the substrate such that the hydrophilic surfaces adjoin each other. Room temperature bonding is then employed to bond the carrier wafer to the substrate. An annealing step is performed and thereafter, the Si-containing substrate of the silicon-on-insulator substrate and the buried oxide region are selectively removed to expose the Si-containing layer.Type: ApplicationFiled: July 24, 2002Publication date: January 29, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Diane C. Boyd, Hussein I. Hanafi, Erin C. Jones, Dominic J. Schepis, Leathen Shi
-
Patent number: 6664598Abstract: A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided. The SOI MOSFET device includes a polysilicon back-gate which controls the threshold voltage of a polysilicon-containing front-gate. The back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.Type: GrantFiled: September 5, 2002Date of Patent: December 16, 2003Assignee: International Business Machines CorporationInventors: Robert H. Dennard, Wilfried E. Haensch, Hussein I. Hanafi
-
Patent number: 6660598Abstract: A sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. In accordance with the method of the present invention, at least one dummy gate region is first formed atop an SOI layer. The dummy gate region includes at least a sacrificial polysilicon region and first nitride spacers located on sidewalls of the sacrificial polysilicon region. Next, an oxide layer that is coplanar with an upper surface of the dummy gate region is formed and then the sacrificial polysilicon region is removed to expose a portion of the SOI layer. A thinned device channel region is formed in the exposed portion of the SOI layer and thereafter inner nitride spacers are formed on exposed walls of the fist nitride spacers. Next, a gate region is formed over the thinned device channel region and then the oxide layer is removed so as to expose thicker portions of the SOI layer than de device channel region.Type: GrantFiled: February 26, 2002Date of Patent: December 9, 2003Assignee: International Business Machines CorporationInventors: Hussein I. Hanafi, Diane C. Boyd, Kevin K. Chan, Wesley Natzle, Leathen Shi
-
Patent number: 6656824Abstract: The present invention provides a method for fabricating low-resistance, sub-0.1 &mgr;m channel T-gate MOSFETs that do not exhibit any poly depletion problems. The inventive method employs a damascene-gate processing step and a chemical oxide removal etch to fabricate such MOSFETs. The chemical oxide removal may be performed in a vapor containing HF and NH3 or a plasma containing HF and NH3.Type: GrantFiled: November 8, 2002Date of Patent: December 2, 2003Assignee: International Business Machines CorporationInventors: Hussein I. Hanafi, Wesley Natzle
-
Publication number: 20030211681Abstract: A sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device having low surface and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.Type: ApplicationFiled: June 13, 2003Publication date: November 13, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hussein I. Hanafi, Diane C. Boyd, Kevin K. Chan, Wesley Natzle, Leathen Shi
-
Patent number: 6635923Abstract: A technique for forming a sub-0.05 &mgr;m channel length double-gated/double channel MOSFET structure having excellent short-channel characteristics as well as the double-gated/double channel MOSFET structure itself is provided herein. The inventive technique utilizes a damascene process for the fabrication of a MOSFET device with double-gate/double channel structure. The gates are present on opposite sides of a silicon film having a vertical thickness of about 80 nm or less which is present in the gate region. The silicon film serves as the vertical channel regions of the structure and connects diffusion regions that are abutting the gate region to each other. In the inventive device, the current is double that of a conventional planar MOSFET with the same physical width due to its dual channel feature.Type: GrantFiled: May 24, 2001Date of Patent: October 21, 2003Assignee: International Business Machines CorporationInventors: Hussein I. Hanafi, Jeffrey J. Brown, Wesley C. Natzle
-
METHOD OF FORMING A FULLY-DEPLETED SOI (SILICON-ON-INSULATOR) MOSFET HAVING A THINNED CHANNEL REGION
Publication number: 20030162358Abstract: A sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.Type: ApplicationFiled: February 26, 2002Publication date: August 28, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hussein I. Hanafi, Diane C. Boyd, Kevin K. Chan, Wesley Natzle, Leathen Shi