Patents by Inventor Jaroslav Hynecek
Jaroslav Hynecek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11037977Abstract: Various embodiments of the present technology may comprise methods and apparatus for an image sensor capable of simultaneous integration of electrons and holes. According to an exemplary embodiment, the image sensor comprises a backside-illuminated hybrid bonded stacked chip image senor comprising a pixel circuit array, and each pixel circuit comprising a charge storage capacitor oriented in a vertical direction in a deep trench isolation region. Both the electrons and holes are integrated (collected) using a global shutter operation, and the charge storage capacitor is used for storing a signal generated by the holes.Type: GrantFiled: August 3, 2018Date of Patent: June 15, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Jaroslav Hynecek
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Publication number: 20210144324Abstract: A backside illuminated (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor array may operate in a rolling shutter scanning mode. The CMOS image sensor may use chip stacking technology with chip-to-chip electrical connections between the top image sensing chip and carrier chip pixel circuits. Each chip-to-chip connection may electrically connect groups of pixels at floating diffusion nodes to a readout circuit. This arrangement allows for small, submicron sized pixels to be formed while using bonding pads that have a larger size. The top light sensing chip pixels do not have transfer gates for lateral charge transfer from photodiodes to the floating diffusion regions. The charge transfer from the photodiode regions is accomplished using a charge punch through technique in a vertical direction. This type of arrangement allows for submicron size pixels in a very large sensor array.Type: ApplicationFiled: November 11, 2019Publication date: May 13, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Jaroslav HYNECEK
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Publication number: 20210136299Abstract: Image sensors may include backside illuminated global shutter pixels that are implemented using stacked substrates. To provide high dynamic range in the pixels, only a predetermined portion of charge that has been generated in the pixel photodiodes is kept and stored in the pixel photodiodes when the pixels are illuminated by high light levels. In the low light level illumination conditions, all of the accumulated charge is stored in the pixel photodiodes, thereby preserving high sensitivity and low noise. Dynamic charge overflow may be used to increase the high dynamic range. To achieve low noise operation in a global shutter scanning mode, dynamic charge overflow may be combined with correlated double sampling techniques. Dynamic charge overflow may be achieved using a transistor-based overflow device or using an n-p-n based overflow device.Type: ApplicationFiled: January 12, 2021Publication date: May 6, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Jaroslav HYNECEK
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Patent number: 10957724Abstract: A back side illuminated image sensor may operate using the single-photon avalanche diode (SPAD) concept in a Geiger mode of operation for single photon detection. The image sensor may be implemented using two layer stacking with a silicon on insulator (SOI) chip. The chip-to-chip electrical connections between the top level image sensing chip and the second level ASIC circuit chip may be realized at each pixel with a single bump connection per pixel. A light level signal may be obtained from pixels that have photon counting capabilities while a distance measurement signal for 3-dimensional imaging may be obtained from pixels that have time-of-flight (ToF) detection capabilities. Both types of pixels may be integrated within the same array and use the same SPAD structure placed on the top chip.Type: GrantFiled: April 18, 2019Date of Patent: March 23, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Jaroslav Hynecek
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Publication number: 20200244900Abstract: Image sensors may include backside illuminated global shutter pixels that are implemented using stacked substrates. To provide high dynamic range in the pixels, only a predetermined portion of charge that has been generated in the pixel photodiodes is kept and stored in the pixel photodiodes when the pixels are illuminated by high light levels. In the low light level illumination conditions, all of the accumulated charge is stored in the pixel photodiodes, thereby preserving high sensitivity and low noise. Dynamic charge overflow may be used to increase the high dynamic range. To achieve low noise operation in a global shutter scanning mode, dynamic charge overflow may be combined with correlated double sampling techniques.Type: ApplicationFiled: July 3, 2019Publication date: July 30, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Jaroslav HYNECEK
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Patent number: 10582140Abstract: An image sensor may be provided with an array of image sensor pixels formed on a substrate having front and back surfaces. Each pixel may have a photodiode that receives light through the back surface, a floating diffusion node, a charge transfer gate, and first and second reset transistor gates. A source follower transistor may have a gate coupled to the floating diffusion node and a source coupled to an addressing transistor. The pixel may be coupled to a column feedback amplifier through the addressing transistor and a column feedback reset path. The amplifier may provide a kTC-reset noise compensation voltage to the reset transistors for storage on a holding capacitor coupled between the floating diffusion and a drain terminal of the source follower. The floating diffusion may be bounded at the front surface by the transfer gate, the reset gate, and p-type doped regions.Type: GrantFiled: October 27, 2017Date of Patent: March 3, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Jaroslav Hynecek
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Patent number: 10574912Abstract: Various embodiments of the present technology may comprise methods and apparatus for an image sensor capable of simultaneous integration of electrons and holes. According to an exemplary embodiment, the image sensor comprises a backside-illuminated hybrid bonded stacked chip image sensor comprising a pixel circuit array, and each pixel circuit comprising a charge storage capacitor oriented in a vertical direction in a deep trench isolation region. Both the electrons and holes are generated and integrated (collected) in the pixel simultaneously, and the charge storage capacitor is used for storing the signal generated by holes in the high light level illuminated pixels.Type: GrantFiled: March 22, 2018Date of Patent: February 25, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Jaroslav Hynecek
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Publication number: 20200043968Abstract: Various embodiments of the present technology may comprise methods and apparatus for an image sensor capable of simultaneous integration of electrons and holes. According to an exemplary embodiment, the image sensor comprises a backside-illuminated hybrid bonded stacked chip image senor comprising a pixel circuit array, and each pixel circuit comprising a charge storage capacitor oriented in a vertical direction in a deep trench isolation region. Both the electrons and holes are integrated (collected) using a global shutter operation, and the charge storage capacitor is used for storing a signal generated by the holes.Type: ApplicationFiled: August 3, 2018Publication date: February 6, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Jaroslav HYNECEK
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METHODS AND APPARATUS FOR AN IMAGE SENSOR CAPABLE OF SIMULTANEOUS INTEGRATION OF ELECTRONS AND HOLES
Publication number: 20190297292Abstract: Various embodiments of the present technology may comprise methods and apparatus for an image sensor capable of simultaneous integration of electrons and holes. According to an exemplary embodiment, the image sensor comprises a backside-illuminated hybrid bonded stacked chip image sensor comprising a pixel circuit array, and each pixel circuit comprising a charge storage capacitor oriented in a vertical direction in a deep trench isolation region. Both the electrons and holes are generated and integrated (collected) in the pixel simultaneously, and the charge storage capacitor is used for storing the signal generated by holes in the high light level illuminated pixels.Type: ApplicationFiled: March 22, 2018Publication date: September 26, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Jaroslav HYNECEK -
Publication number: 20190244986Abstract: A back side illuminated image sensor may operate using the single-photon avalanche diode (SPAD) concept in a Geiger mode of operation for single photon detection. The image sensor may be implemented using two layer stacking with a silicon on insulator (SOI) chip. The chip-to-chip electrical connections between the top level image sensing chip and the second level ASIC circuit chip may be realized at each pixel with a single bump connection per pixel. A light level signal may be obtained from pixels that have photon counting capabilities while a distance measurement signal for 3-dimensional imaging may be obtained from pixels that have time-of-flight (ToF) detection capabilities. Both types of pixels may be integrated within the same array and use the same SPAD structure placed on the top chip.Type: ApplicationFiled: April 18, 2019Publication date: August 8, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Jaroslav HYNECEK
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Patent number: 10312275Abstract: A back side illuminated image sensor may operate using the single-photon avalanche diode (SPAD) concept in a Geiger mode of operation for single photon detection. The image sensor may be implemented using two layer stacking with a silicon on insulator (SOI) chip. The chip-to-chip electrical connections between the top level image sensing chip and the second level ASIC circuit chip may be realized at each pixel with a single bump connection per pixel. A light level signal may be obtained from pixels that have photon counting capabilities while a distance measurement signal for 3-dimensional imaging may be obtained from pixels that have time-of-flight (ToF) detection capabilities. Both types of pixels may be integrated within the same array and use the same SPAD structure placed on the top chip.Type: GrantFiled: April 25, 2017Date of Patent: June 4, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Jaroslav Hynecek
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Patent number: 10186535Abstract: Electronic devices may include High Dynamic Range (HDR) complementary metal-oxide-semiconductor (CMOS) image sensor arrays that are illuminated from the back side of the substrate and operate in a rolling shutter (RS) scanning mode. An image sensor may include stacked chips to improve image sensor performance. For example, by stacking photodiodes on top of each other and using dichroic dielectric layers in chip-to-chip isolation, sensor sensitivity may be increased, Moiré effect may be reduced, and the overall image sensor performance may be improved. Image sensors may include a charge sensing and charge storing scheme where charge generated by low incident light levels is transferred onto a charge sensing node of an in-pixel inverting feedback amplifier and charge generated by high incident light levels overflows a certain potential barrier built in the pixel, is stored on capacitors, and is sensed by a source follower.Type: GrantFiled: September 19, 2016Date of Patent: January 22, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jaroslav Hynecek, Vladimir Korobov
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Patent number: 10141356Abstract: An image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a floating diffusion node, and a charge transferring transistor. The charge transferring transistor may be a dual gate transistor having first and second gate terminals. A suitable bias may be applied to the second gate terminal to alter the capacitance of the floating diffusion node. The amount of electrons that may be accommodated by the floating diffusion node may be altered with application of a varying voltage level bias at the second gate terminal. By implementing a dual gate transistor, dynamic range compression and anti-blooming charge overflow may be implemented directly in the pixel to reduce image sensor pixel size and cost.Type: GrantFiled: April 11, 2016Date of Patent: November 27, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Jaroslav Hynecek
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Publication number: 20180308881Abstract: A back side illuminated image sensor may operate using the single-photon avalanche diode (SPAD) concept in a Geiger mode of operation for single photon detection. The image sensor may be implemented using two layer stacking with a silicon on insulator (SOI) chip. The chip-to-chip electrical connections between the top level image sensing chip and the second level ASIC circuit chip may be realized at each pixel with a single bump connection per pixel. A light level signal may be obtained from pixels that have photon counting capabilities while a distance measurement signal for 3-dimensional imaging may be obtained from pixels that have time-of-flight (ToF) detection capabilities. Both types of pixels may be integrated within the same array and use the same SPAD structure placed on the top chip.Type: ApplicationFiled: April 25, 2017Publication date: October 25, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Jaroslav HYNECEK
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Patent number: 10070079Abstract: A global shutter image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a charge storage region, low light level circuitry and high light level circuitry. During high light level conditions, some charge generated by the photodiode may be diverted to the high light level circuitry and the remainder may be transferred to the low light level circuitry. During low light level conditions, all of the generated charge may be transferred to the low light level circuitry. A light shielding structure may be formed over the charge storage region. The circuit components of each pixel may be divided between first and second chips. By forming the components on separate chips and by implementing high light level circuitry, the size of the charge storage region may be reduced while preserving the high dynamic range and low noise of the image sensor during all illumination conditions.Type: GrantFiled: January 30, 2017Date of Patent: September 4, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jaroslav Hynecek, Bartosz Piotr Banachowicz
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Patent number: 10051214Abstract: An image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a charge storage region, and a charge overflow circuit. The charge storage region may be used to operate the image sensor array in global shutter mode. During high light level illumination, the charge overflow circuit may divert charge away from the photodiode such that only a predetermined portion of the accumulated charge remains in the photodiode. During low light level illumination all of the accumulated charge may be stored in the pixel photodiode. The charge overflow circuit may include a transistor and a resistor or capacitor. By implementing a charge overflow circuit, the size of the charge storage region may be reduced while still preserving the high dynamic range and low noise of the image sensor during all light illumination conditions.Type: GrantFiled: June 9, 2017Date of Patent: August 14, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Jaroslav Hynecek
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Publication number: 20180220086Abstract: A global shutter image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a charge storage region, low light level circuitry and high light level circuitry. During high light level conditions, some charge generated by the photodiode may be diverted to the high light level circuitry and the remainder may be transferred to the low light level circuitry. During low light level conditions, all of the generated charge may be transferred to the low light level circuitry. A light shielding structure may be formed over the charge storage region. The circuit components of each pixel may be divided between first and second chips. By forming the components on separate chips and by implementing high light level circuitry, the size of the charge storage region may be reduced while preserving the high dynamic range and low noise of the image sensor during all illumination conditions.Type: ApplicationFiled: January 30, 2017Publication date: August 2, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jaroslav HYNECEK, Bartosz Piotr BANACHOWICZ
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Patent number: 10020338Abstract: A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer disposed on the backside passivation layer.Type: GrantFiled: November 18, 2015Date of Patent: July 10, 2018Assignee: INTELLECTUAL VENTURES II LLCInventors: Jaroslav Hynecek, Leonard Forbes, Homayoon Haddad, Thomas Joy
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Patent number: 9991306Abstract: In one form, a hybrid bonded image sensor comprises a photodiode chip, a circuit carrying chip, and an interconnection. The photodiode chip provides charge to a first floating diffusion in response to incident light, wherein the first floating diffusion is coupled to a first terminal on a first surface of the photodiode chip. The circuit carrying chip has a first terminal aligned with the first terminal of the photodiode chip, the circuit carrying chip forming an output voltage based on charge transferred on the first floating diffusion sensed from the first terminal thereof. The interconnection connects the first terminal of the photodiode chip to the first terminal of the circuit carrying chip.Type: GrantFiled: May 13, 2016Date of Patent: June 5, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jaroslav Hynecek, Vladimir Korobov
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Patent number: 9936150Abstract: Imaging pixels may be operated in a rolling shutter scanning mode. Charge signal that is generated on a first chip may be capacitively coupled to signal processing circuits on a second chip. A capacitor may be placed in the signal path that provides signal coupling between the chips and stores overflow charge from pixels that have been exposed to high light level illumination. This enables high dynamic range using only a single charge integration time. The pixel may include an in-pixel negative feedback amplifier. The chip-to-chip electrical connections between the first and second chips may be realized at each pixel as a hybrid bond with a single bond per pixel. Image sensors fabricated using this technology may have small size pixels, high resolution, high dynamic range, and a single charge integration time.Type: GrantFiled: June 8, 2016Date of Patent: April 3, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Jaroslav Hynecek