Patents by Inventor Jaroslav Hynecek

Jaroslav Hynecek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130237004
    Abstract: A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer disposed on the backside passivation layer.
    Type: Application
    Filed: April 9, 2013
    Publication date: September 12, 2013
    Inventors: Jaroslav Hynecek, Leonard Forbes, Homayoon Haddad, Thomas Joy
  • Patent number: 8508638
    Abstract: The present invention describes in detail the solid-state image sensor, specifically the image sensors pixel that has three transistors, high sensitivity, low reset noise, and low dark current. Low reset noise is achieved by parametrically changing the voltage dependent capacitance of the charge detection node in such a manner that during reset the charge detection node capacitance is low while during sensing and integration cycles the charge detection node capacitance is high. This feature thus results in high dynamic range, which is important for sensors using very small pixels. The low dark current generation is achieved by quenching the interface states by placing a p+ implant near the silicon-silicon dioxide interface.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: August 13, 2013
    Assignee: Intellectual Ventures II LLC
    Inventor: Jaroslav Hynecek
  • Patent number: 8497546
    Abstract: Image sensor arrays may include bulk-charge-modulated-device (BCMD) sensor pixels. The BCMD sensor pixels may be used in back-side-illuminated (BSI) image sensors. A BCMD sensor pixel need not include a dedicated addressing transistor. The BCMD sensor pixel may include a gated drain reset (GDR) structure that is used to perform reset operations. The GDR structure may be shared among multiple pixels, which provides increased charge storage capacity for high resolution image sensors. A negative back body bias may be applied to the BCMD pixel array, allowing the depletion region under each BCMD pixel to extend all the way to the back silicon surface. Extending the depletion region by negatively biasing the back silicon surface may serve to minimize pixel crosstalk.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: July 30, 2013
    Assignee: Aptina Imaging Corporation
    Inventor: Jaroslav Hynecek
  • Patent number: 8487349
    Abstract: The invention describes in detail the structure of a CMOS image sensor pixel that senses color of impinging light without having absorbing filters placed on its surface. The color sensing is accomplished by having a vertical stack of three-charge detection nodes placed in the silicon bulk, which collect electrons depending on the depth of their generation. The small charge detection node capacitance and thus high sensitivity with low noise is achieved by using fully depleted, potential well forming, buried layers instead of undepleted junction electrodes. Two embodiments of contacting the buried layers without substantially increasing the node capacitances are presented.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: July 16, 2013
    Assignee: Foveon, Inc.
    Inventors: Jaroslav Hynecek, Richard B. Merrill, Russel A. Martin
  • Patent number: 8471315
    Abstract: The invention describes a solid-state CMOS image sensor array and in particular describes in detail image sensor array pixels having global and rolling shutter capabilities that are using a dual channel transfer-storage gate for charge transfer from a PD to a TX gate well and from the TX gate well onto a FD. The dual channels are stacked above each other where a shallow charge channel is used to drain surface generated dark current away from the pixel structure, while a buried bulk channel provides for standard charge transfer and storage functions. This feature thus improves the sensor noise performance and prevents signal contamination and various shading effects caused by the dark current buildup during a prolonged charge storage sequence in pixels of image sensor arrays using the global shutter mode of operation. Several embodiment of this concept are described including pixels which utilize shared circuitry, a complete PD reset capability, and an efficient anti-blooming control.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: June 25, 2013
    Assignee: Aptina Imaging Corporation
    Inventors: Jaroslav Hynecek, Hirofumi Komori
  • Patent number: 8471310
    Abstract: Image sensor arrays may include image sensor pixels each having at least one back-gate-modulated vertical transistor. The back-gate-modulated vertical transistor may be used as a source follower amplifier. An image sensor pixel need not include an address transistor. The image sensor pixel with the back-gate-modulated vertical source follower transistor may exhibit high fill factor, large charge storage capacity, and has as few as two row control lines and two column control lines per pixel. This can be accomplished without pixel circuit sharing. The pixel may also provide direct photo-current sensing capabilities. The ability to directly sense photo-current may facilitate fast adjustment of sensor integration time. Fast adjustment of sensor integration time may be advantageous in automotive and endoscopic applications in which the time available for the correction of integration time is limited.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: June 25, 2013
    Assignee: Aptina Imaging Corporation
    Inventor: Jaroslav Hynecek
  • Publication number: 20130153973
    Abstract: Image sensor pixels are provided having junction gate photodiodes. A group of pixels may have a shared floating diffusion region and a shared source-follower transistor. The source-follower transistor may be a JFET source-follower with a gate that forms the floating diffusion region. The JFET source-follower may be a vertical or lateral JFET. A reset diode may be forward-biased to reset the floating diffusion region. Each pixel may have a JFET that serves as a charge transfer barrier between the junction gate photodiode and the floating diffusion region. The charge transfer barrier JFET may be a lateral JFET. The image sensor pixels may be formed without any metal-oxide-semiconductor devices.
    Type: Application
    Filed: April 18, 2012
    Publication date: June 20, 2013
    Applicant: Aptina Imaging Corporation
    Inventor: Jaroslav Hynecek
  • Publication number: 20130146747
    Abstract: An image sensor pixel suitable for use in a back-side-illuminated or a front-side-illuminated sensor arrangement is provided. The image sensor pixel may be a small size pixel that includes a source follower implemented using a vertical junction field effect (JFET) transistor. The vertical JFET source follower may be integrated directly into the floating diffusion node, thereby eliminating excess metal routing and pixel area typically allocated for the source follower in conventional pixel configurations. Pixel area may instead be allocated for increasing the charge storage capacity of the photodiode or can be used to reduce pixel size while maintaining pixel performance. Using a vertical junction field effect transistor in this way simplifies pixel addressing operations and minimizes random telegraph signal (RTS) noise associated with small size metal-oxide-semiconductor (MOS) transistors.
    Type: Application
    Filed: May 21, 2012
    Publication date: June 13, 2013
    Inventor: Jaroslav Hynecek
  • Publication number: 20130143351
    Abstract: A pixel of an image sensor, the pixel includes a floating diffusion node to sense photo-generated charge, a reset diode to reset the floating diffusion node in response to a reset signal, and a set diode to set the floating diffusion node.
    Type: Application
    Filed: January 9, 2013
    Publication date: June 6, 2013
    Applicant: CROSSTEK CAPITAL, LLC.
    Inventor: Jaroslav Hynecek
  • Patent number: 8420438
    Abstract: A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer disposed on the backside passivation layer.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: April 16, 2013
    Assignee: Intellectual Ventures II, LLC
    Inventors: Jaroslav Hynecek, Leonard Forbes, Homayoon Haddad, Thomas Joy
  • Patent number: 8409903
    Abstract: An image sensor comprises a substrate of a first conductivity type. First and second pixels are arrayed over the substrate. A potential barrier is formed in a region of the substrate corresponding to the first pixel but not in a region of the substrate corresponding to the second pixel. The second pixel is responsive to a color having a wavelength longer than the color to which the first pixel is responsive. The potential barrier is doped with dopants by a high energy ion implantation dopants or by an ion implantation or diffusion during epitaxial growth of the P-type epitaxial layer.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: April 2, 2013
    Assignee: Intellectual Ventures II L.L.C.
    Inventor: Jaroslav Hynecek
  • Patent number: 8373781
    Abstract: A pixel of an image sensor includes only two signal lines per pixel, a pinned photodiode for sensing light, a floating base bipolar transistor, and no reset and address transistors. The floating base bipolar transistor provides the pixel with a gain, which can increase pixel sensitivity and reduce noise. The pixel also incorporates a vertical blooming control structure for an efficient blooming suppression. The output terminals of the pixel are coupled to a common column output line terminated by a special current sensing correlated double sampling circuit, which is used for subtraction of emitter leakage current. Based on this structure, the pixel has high sensitivity, high response uniformity, low noise, reduced size, and efficient layout.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: February 12, 2013
    Assignee: Intellectual Ventures II LLC
    Inventor: Jaroslav Hynecek
  • Publication number: 20130026345
    Abstract: A pixel and a pixel array of an image sensor device of the present invention have small pixel sizes by resetting sensed charge using a diode built vertically above a substrate. The pixel and the pixel array also have low noise performance by using a JFET as a source follower transistor for sensing charge. The pixel includes a floating diffusion node configured to sense photo-generated charge, a reset diode configured to reset the floating diffusion node in response to a reset signal, and a junction field effect transistor configured to output a signal having an output voltage level corresponding to a charge level of the floating diffusion node.
    Type: Application
    Filed: July 31, 2012
    Publication date: January 31, 2013
    Inventor: Jaroslav Hynecek
  • Patent number: 8362532
    Abstract: A pixel of an image sensor, the pixel includes a floating diffusion node to sense photo-generated charge, a reset diode to reset the floating diffusion node in response to a reset signal, and a set diode to set the floating diffusion node.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: January 29, 2013
    Assignee: Intellectual Ventures II LLC
    Inventor: Jaroslav Hynecek
  • Publication number: 20120295386
    Abstract: A stratified photodiode for high resolution CMOS image sensors implemented with STI technology is provided. The photodiode includes a semi-conductive layer of a first conductivity type, multiple doping regions of a second conductivity type, multiple doping regions of the first conductivity type, and a pinning layer. The multiple doping regions of the second conductivity type are formed to different depths in the semi-conductive layer. The multiple doping regions of the first conductivity type are disposed between the multiple doping regions of the second conductivity type and form multiple junction capacitances without full depletion. In particular, the stratified doping arrangement allows the photodiode to have a small size, high charge storage capacity, low dark current, and low operation voltages.
    Type: Application
    Filed: July 31, 2012
    Publication date: November 22, 2012
    Applicant: Intellectual Ventures II LLC (remove and reenter with front before filing)
    Inventor: Jaroslav Hynecek
  • Publication number: 20120273654
    Abstract: The present invention provides a junction gate photo-diode (JGP) pixel that includes a JGP accumulating charge in response to impinging photons. The JGP is positioned on a substrate and includes a top n layer, a middle p layer and a bottom n layer forming a n-p-n junction, and a control terminal coupled to the top n layer. Also includes is a floating diffusion (FD) positioned on the substrate and coupled to a pixel output line through an amplifier. Also includes is a pinned barrier (PB) and a storage gate (SG) positioned on the substrate between the JGP and the FD. The PB temporarily blocks charge transfer between the JGP and the FD, and the SG stores the accumulated charge from the JGP, and transfers the stored charge to the FD for readout.
    Type: Application
    Filed: August 16, 2011
    Publication date: November 1, 2012
    Applicant: APTINA IMAGING CORPORATION
    Inventors: Jaroslav Hynecek, Hirofumi Komori
  • Publication number: 20120273653
    Abstract: The present invention relates to a junction gate photo-diode (JGP) pixel that includes a JGP for accumulating charge in response to impinging photons. The JGP is positioned on a substrate and includes a top n layer, a middle p layer and a bottom n layer forming a n-p-n junction, and a control terminal coupled to the top n layer. Also included is a floating diffusion (FD) positioned on the substrate and coupled to a pixel output line through an amplifier. Also included is a pinned barrier (PB) positioned on the substrate between the JGP and the FD, the PB temporarily blocks charge transfer between the JGP and the FD. The accumulated charge is transferred from the JGP to FD by applying a control voltage to the JGP control terminal.
    Type: Application
    Filed: August 16, 2011
    Publication date: November 1, 2012
    Applicant: APTINA IMAGING CORPORATION
    Inventors: Jaroslav HYNECEK, Hirofumi Komori, Xia Zhao
  • Patent number: 8274587
    Abstract: Image sensors having image sensor pixels with stacked photodiodes are provided. An image sensor pixel may include a shallow potential well located in a shallow implant region and a deep potential well located in a deep implant region. The shallow implant region and the deep implant region may be separated by a potential barrier. The image sensor pixel may have a given transfer gate to transfer charge from the shallow well to a floating diffusion node. The image sensor pixel may have an additional transfer gate to transfer charge from the deep well to the shallow well via a vertical transfer region located under the additional transfer gate. Image sensor pixels formed using this structure may exhibit higher pixel densities, higher image resolution, and higher sensitivity.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: September 25, 2012
    Assignee: Aptina Imaging Corporation
    Inventor: Jaroslav Hynecek
  • Patent number: 8258560
    Abstract: This describes color filter arrangements for image sensor arrays that are formed using image sensor pixels with stacked photo-diodes. The stacked photo-diodes may include first and second photo-diodes and may have the ability to separate color signal according to the depth of carrier generation in a silicon substrate. A single color filter may be formed over the stacked photo-diodes to provide full red-green-blue sensing capability. Charge drain regions may also be formed at different depths in the silicon substrate. If the charge drain regions are formed beneath the stacked photo-diodes in the substrate, full red-green-blue color sensing may be achieved without the use of color filters.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: September 4, 2012
    Assignee: Aptina Imaging Corporation
    Inventor: Jaroslav Hynecek
  • Patent number: 8247853
    Abstract: A stratified photodiode for high resolution CMOS image sensors implemented with STI technology is provided. The photodiode includes a semi-conductive layer of a first conductivity type, multiple doping regions of a second conductivity type, multiple doping regions of the first conductivity type, and a pinning layer. The multiple doping regions of the second conductivity type are formed to different depths in the semi-conductive layer. The multiple doping regions of the first conductivity type are disposed between the multiple doping regions of the second conductivity type and form multiple junction capacitances without full depletion. In particular, the stratified doping arrangement allows the photodiode to have a small size, high charge storage capacity, low dark current, and low operation voltages.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: August 21, 2012
    Assignee: Intellectual Ventures II LLC
    Inventor: Jaroslav Hynecek