Abstract: The invention disclosure describes pixels arranged into CMOS image sensor arrays that may be back side illuminated and may operate in a global shutter mode. The image sensor pixels may also be front side illuminated. The pixel charge storage sites for the global shutter operation are formed by floating diffusions that are small and do not collect a significant number of stray charge, which contributes to the sensor's high shutter efficiency. The floating diffusions are reset by an active reset circuit that significantly reduces generation of kTC reset noise. The active reset circuit consists of an in-pixel inverting amplifier formed by a p-channel gain transistor with an n-channel transistor load, and a feedback reset transistor connected from the amplifier output to the amplifier input, which is the FD node. The active reset circuit does not utilize a significant portion of the pixel area and has low power consumption.

Abstract: An image sensor may be provided with an array of image pixels formed on a substrate having front and back surfaces. Each pixel may have a photodiode that receives light through the back surface, a floating diffusion node, and a charge transfer gate. The floating diffusion node may be formed in the center of the photodiode and may be surrounded by the charge transfer gate at the front surface. The charge transfer gate may isolate the floating diffusion node from the surrounding photodiode. The pixel may include reset transistor gates, an addressing transistor gate, and a source follower transistor arranged about the periphery of the photodiode. By centering the floating diffusion node and charge transfer gate within the photodiode, the image pixels may have improved shutter efficiency and charge transfer efficiency relative to pixels having floating diffusion nodes at non-centralized locations.

Abstract: An image sensor includes at least one pixel with a transfer gate that is controllable among at least three biasing conditions, including a first biasing condition in which electrons are transferable from a photodiode to a potential well under the transfer gate, a second biasing condition in which the electrons are confined in the potential well under the transfer gate, and a third biasing condition in which the electrons are transferable out of the potential well under the transfer gate. The pixel includes a p+ type doped barrier implant located at least partially under a portion of the transfer gate, and a pinned charge transfer barrier located on the opposite side of the transfer gate from the photodiode that includes a p+ type doped region and an n-type doped region. The image sensor can operate in a global shutter mode and/or a rolling shutter mode.

Abstract: An image sensor may be provided with an array of image sensor pixels formed on a substrate having front and back surfaces. Each pixel may have a photodiode that receives light through the back surface, a floating diffusion node, a charge transfer gate, and first and second reset transistor gates. A source follower transistor may have a gate coupled to the floating diffusion node and a source coupled to an addressing transistor. The pixel may be coupled to a column feedback amplifier through the addressing transistor and a column feedback reset path. The amplifier may provide a kTC-reset noise compensation voltage to the reset transistors for storage on a holding capacitor coupled between the floating diffusion and a drain terminal of the source follower. The floating diffusion may be bounded at the front surface by the transfer gate, the reset gate, and p-type doped regions.

Abstract: An image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a floating diffusion node, and charge transfer gate. An amplifying transistor may have a gate terminal coupled to the floating diffusion and a drain terminal coupled to an output node. The amplifying transistor may provide signal corresponding to transferred charge with a greater than unity voltage gain. A negative voltage feedback capacitor having variable capacitance may be coupled between the output node and the floating diffusion node thereby increasing the pixel dynamic range. A reset transistor may be coupled between the floating diffusion and output node. The amplifying transistor may include a p-channel transistor formed within a mini n-well region of the pixel or an n-channel transistor formed within a mini p-well region. The pixel may have increased storage capacity and dynamic range relative to conventional designs.

Abstract: An image sensor may include image sensor pixels formed on a substrate. Each pixel may have a photodiode, a floating diffusion node, and charge transfer gate. The pixel may include an n? type doped well region and a p-channel MOS source follower transistor formed within the n-well region. An n-channel MOS reset transistor may be coupled between the floating diffusion region and a bias voltage column line and may have a drain terminal that overlaps with the n-well region. If desired, the pixel may include a p-channel JFET source follower transistor formed within the floating diffusion region on the substrate and an n-channel MOSFET reset transistor coupled to the floating diffusion. The polarities of the doping in the substrate on which the pixels are formed may be reversed. The pixel may be formed without row select transistors to increase photodiode area and charge storage capacity.

Abstract: The invention describes image sensor array pixels with global and rolling shutter capabilities that utilize multiple BCMD transistors for storing and sensing charge for a single photodiode. This configuration improves the Dynamic Range (DR) of the sensor, by allowing sensing different image signals from a single pixel without saturation, a low level signal with long integration time followed by a high level signal with short integration time. Signal processing circuits can process these signals into a single Wide Dynamic Range (WDR) output. Further disclosed are pixels that use multiple-gate BCMD transistors for charge storage and sensing having multiple concentric gates, which allows changing the conversion gain of the BCMD transistors. Variable conversion gain is a useful feature when building WDR sensors since low conversion gain and high well capacity allows detection of high level signals and, at the same time, low level signals with high conversion gain and low noise.

Abstract: A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer disposed on the backside passivation layer.

Abstract: A back side illuminated image sensor may be provided with an array of image sensor pixels. Each image sensor pixel may include a substrate having a front surface and a back surface. The image sensor pixels may have a charge storage region formed at the back surface and a charge readout node formed at the front surface of the substrate. The image sensor pixels may receive image light at the back surface of the substrate. Photo-generated charge may be accumulated at the charge storage region during a charge integration cycle. Upon completion of the charge integration cycle, a transfer gate formed at the front surface may be pulsed high to move the charge from the charge storage region to the charge readout node. The charge may be converted to a voltage at the charge readout node and may be read out using a rolling shutter readout mode.

Abstract: An image sensor operable in global shutter mode ma include small pixels with high charge storage capacity, low dark current, and no image lag. Storage capacity of a photodiode and a charge storage diode may be increased by placing a p+ type doped layer under the photodiode and the charge storage diode. The p+ type doped layer ma include an opening for allowing photo-generated charge carriers to flow from the silicon bulk to the charge storage well located near the surface of the photodiode. A compensating n? type doped implant may be formed in the opening. Image lag is prevented by placing a p? type doped region under the p+ type doped photodiode pinning layer and aligned with the opening. The p+ type doped layer may extend under the entire pixel array.

Abstract: Pixels for solid-state CMOS image sensor arrays may be provided that have a lateral blooming control structure incorporated in them. The lateral blooming control structure is built as a separate structure from the charge transfer gate and it is fabricated in a self-aligned manner, which is particularly suitable for incorporating into small size pixels. The blooming control structure can be used for backside or for front side illuminated image sensors. When the lateral blooming control structure is provided with a separate bias means, it may also be used for the complete or partial charge removal from the photodiode and thus used in pixels that are designed for global shutter operation.

Abstract: An image sensor may include an array of pixels that, do not include any source follower, reset, or addressing transistors, which helps to increase pixel well capacity, reduces or eliminates random telegraph signal (RTS) noise, and reduces undesirable dark current. Charge to voltage conversion may be performed by charge detection circuitry that is external to the array of pixels. The charge detection circuitry may include amplifier circuitry such as an operational amplifier and may be located at the periphery of the array of pixels or on a different semiconductor substrate. By locating the charge detection circuitry outside of the array of pixels, additional flexibility may be provided for the charge detection circuitry. The charge detection circuitry may be provided with switchable gain or with non-linear charge to voltage conversion capability.

Abstract: A back side illuminated image sensor may be provided with an array of image sensor pixels. Each pixel may include a substrate having a front surface and a back surface. The pixels may have a charge storage region at the back surface and a charge readout node at the front surface of the substrate. The pixels may receive light at the back surface. Photo-generated charge may be accumulated at the charge storage region during a charge integration cycle. Upon completion of the charge integration cycle, a transfer gate formed at the front surface may be pulsed high to move the charge from the charge storage region to the charge readout node using a global shutter algorithm. The pixels may include two reset transistors that are coupled to column feedback amplifier circuitry for mitigating kTC-reset noise when the pixels are operated in a global shutter mode.

Abstract: A pixel of an image sensor, the pixel includes a floating diffusion node to sense photo-generated charge, a reset diode to reset the floating diffusion node in response to a reset signal, and a set diode to set the floating diffusion node.

Abstract: An image sensor includes at least one pixel with a transfer gate that is controllable among at least three biasing conditions, including a first biasing condition in which electrons are transferable from a photodiode to a potential well under the transfer gate, a second biasing condition in which the electrons are confined in the potential well under the transfer gate, and a third biasing condition in which the electrons are transferable out of the potential well under the transfer gate. The pixel includes a p+ type doped barrier implant located at least partially under a portion of the transfer gate, and a pinned charge transfer barrier located on the opposite side of the transfer gate from the photodiode that includes a p+ type doped region and an n-type doped region. The image sensor can operate in a global shutter mode and/or a rolling shutter mode.

Abstract: The invention describes image sensor array pixels with global and rolling shutter capabilities that utilize multiple BCMD transistors for storing and sensing charge for a single photodiode. This configuration improves the Dynamic Range (DR) of the sensor, by allowing sensing different image signals from a single pixel without saturation, a low level signal with long integration time followed by a high level signal with short integration time. Signal processing circuits can process these signals into a single Wide Dynamic Range (WDR) output. Further disclosed are pixels that use multiple-gate BCMD transistors for charge storage and sensing having multiple concentric gates, which allows changing the conversion gain of the BCMD transistors. Variable conversion gain is a useful feature when building WDR sensors since low conversion gain and high well capacity allows detection of high level signals and, at the same time, low level signals with high conversion gain and low noise.

Abstract: An image sensor operable in global shutter mode ma include small pixels with high charge storage capacity, low dark current, and no image lag. Storage capacity of a photodiode and a charge storage diode may be increased by placing a p+ type doped layer under the photodiode and the charge storage diode. The p+ type doped layer ma include an opening for allowing photo-generated charge carriers to flow from the silicon bulk to the charge storage well located near the surface of the photodiode. A compensating n? type doped implant may be formed in the opening. Image lag is prevented by placing a p? type doped region under the p+ type doped photodiode pinning layer and aligned with the opening. The p+ type doped layer may extend under the entire pixel array.

Abstract: An image sensor having an array of pixels and a silicon substrate may be provided. In one embodiment, the array of pixels may have pixels of equal charge storage capacity but with varying sizes and thus varying sensitivities. For example, a first pixel may have a larger charge-generating volume than a second pixel. In another suitable embodiment, the charge storage capacity of the image sensor pixels may be varied while the charge-generating volume remains the same. These configurations are achieved by placing a p+ type doped layer in the silicon substrate close to and parallel to the surface of the array. The p+ type doped layer may include a plurality of openings to allow photo-generated carriers to flow from the silicon bulk to the charge storage wells located near the surface of the substrate.

Abstract: The invention describes in detail a solid-state CMOS image sensor, specifically a CMOS image sensor pixel that has stacked photo-sites, high sensitivity, and low dark current. The pixels have incorporated therein special potential barriers under the standard pinned photodiode region that diverts the photo-generated electrons from a deep region within the silicon bulk to separate storage structures located at the surface of the silicon substrate next to the pinned photodiode. The storage structures are p channel BCMD transistors that are biased to a low dark current generation mode during a charge integration period. The signal readout from the BCMD is nondestructive, therefore, without kTC noise generation. Thus a single pixel is capable of detecting several color-coded signals while using fewer or without using any light absorbing color filters on top of the pixel.

Abstract: An image sensor pixel suitable for use in a back-side-illuminated or a front-side-illuminated sensor arrangement is provided. The image sensor pixel may be a small size pixel that includes a source follower implemented using a vertical junction field effect (JFET) transistor. The vertical JFET source follower may be integrated directly into the floating diffusion node, thereby eliminating excess metal routing and pixel area typically allocated for the source follower in conventional pixel configurations. Pixel area may instead be allocated for increasing the charge storage capacity of the photodiode or can be used to reduce pixel size while maintaining pixel performance. Using a vertical junction field effect transistor in this way simplifies pixel addressing operations and minimizes random telegraph signal (RTS) noise associated with small size metal-oxide-semiconductor (MOS) transistors.