Abstract: The invention describes a solid-state CMOS image sensor array and discloses image sensor array pixels with global and rolling shutter capabilities that utilize multiple BCMD transistors for a single photodiode, for charge storage and sensing. Thus, the valuable pixel area saved by employing the BCMD transistor for charge storage and sensing is used by placing several BCMD transistors coupled to one photodiode. This increases the Dynamic Range (DR) of the sensor, since the same photodiode can integrate charge for different integration times, both long and short. This allows sensing of two different image signals from a single pixel without saturation, a low level signal with long integration time followed by a high level signal with short integration time. The signal processing circuits located at the periphery of the array can then process these signals into a single Wide Dynamic Range (WDR) output.

Abstract: An image sensor includes at least one pixel with a transfer gate that is controllable among at least three biasing conditions, including a first biasing condition in which electrons are transferable from a photodiode to a potential well under the transfer gate, a second biasing condition in which the electrons are confined in the potential well under the transfer gate, and a third biasing condition in which the electrons are transferable out of the potential well under the transfer gate. The pixel includes a p+ type doped barrier implant located at least partially under a portion of the transfer gate, and a pinned charge transfer barrier located on the opposite side of the transfer gate from the photodiode that includes a p+ type doped region and an n-type doped region. The image sensor can operate in a global shutter mode and/or a rolling shutter mode.

Abstract: Pixels for solid-state CMOS image sensor arrays may be provided that have a lateral blooming control structure incorporated in them. The lateral blooming control structure is built as a separate structure from the charge transfer gate and it is fabricated in a self-aligned manner, which is particularly suitable for incorporating into small size pixels. The blooming control structure can be used for backside or for front side illuminated image sensors. When the lateral blooming control structure is provided with a separate bias means, it may also be used for the complete or partial charge removal from the photodiode and thus used in pixels that are designed for global shutter operation.

Abstract: An image sensor having small pixels with high charge storage capacity, low dark current, no image lag, and good blooming control may be provided. The high charge storage capacity is achieved by placing a p+ type doped layer under the pixel charge storage region with an opening in it for allowing photo-generated charge carriers to flow from the silicon hulk to the charge storage well located near the surface of the photodiode. A compensating n-type doped implant may be formed in the opening. Image lag is prevented by placing a p? type doped region under the p+ type doped photodiode pinning layer and aligned with the opening. Blooming control is achieved by adjusting the length of the transfer gate in the pixel and thereby adjusting the punch-through potential under the gate.

Abstract: A reset transistor includes a floating diffusion region for detecting a charge, a junction region for draining the charge, a gate for controlling a transfer of the charge from the floating diffusion region to the junction region upon receipt of a reset signal, and a potential well incorporated underneath the gate.

Abstract: A pixel and a pixel array of an image sensor device of the present invention have small pixel sizes by resetting sensed charge using a diode built vertically above a substrate. The pixel and the pixel array also have low noise performance by using a JFET as a source follower transistor for sensing charge. The pixel includes a floating diffusion node configured to sense photo-generated charge, a reset diode configured to reset the floating diffusion node in response to a reset signal, and a junction field effect transistor configured to output a signal having an output voltage level corresponding to a charge level of the floating diffusion node.

Abstract: The invention describes the solid-state image sensor array and in particular describes in detail the junction gate BCMD pixel sensor array that can be used in the back side illuminated mode as well as in the front side illuminated mode. The pixels generally do not need addressing transistors and the reset is accomplished in a vertical direction to the junction gate, so no additional reset transistor is needed for this purpose. As a result of this innovation the pixel maintains large charge storage capacity when its size is reduced, has low noise due to the nondestructive charge readout, and no RTS noise. The pixel interface generated dark current is also drained to the gate, so the image sensor array operates with very low dark current noise even at high temperatures. The junction gate also serves as a drain for the overflow charge.

Abstract: A pixel of an image sensor includes only two signal lines per pixel, a pinned photodiode for sensing light, a floating base bipolar transistor, and no reset and address transistors. The floating base bipolar transistor provides the pixel with a gain, which can increase pixel sensitivity and reduce noise. The pixel also incorporates a vertical blooming control structure for an efficient blooming suppression. The output terminals of the pixel are coupled to a common column output line terminated by a special current sensing correlated double sampling circuit, which is used for subtraction of emitter leakage current. Based on this structure, the pixel has high sensitivity, high response uniformity, low noise, reduced size, and efficient layout.

Abstract: The invention describes a solid-state CMOS image sensor array and in particular describes in detail the image sensor array pixels, with global and rolling shutter capabilities, that utilize charge storage gates located on top of a pinned photodiode. The sensor array is illuminated from the back side and the location of the storage gate on top of the pinned photodiode saves valuable pixel area, which does not compromise the Dynamic Range of the image sensor.

Abstract: Image sensor pixels are provided having junction gate photodiodes. A group of pixels may have a shared floating diffusion region and a shared source-follower transistor. The source-follower transistor may be a JFET source-follower with a gate that forms the floating diffusion region. The JFET source-follower may be a vertical or lateral JFET. A reset diode may be forward-biased to reset the floating diffusion region. Each pixel may have a JFET that serves as a charge transfer barrier between the junction gate photodiode and the floating diffusion region. The charge transfer barrier JFET may be a lateral JFET. The image sensor pixels may be formed without any metal-oxide-semiconductor devices.

Abstract: An image sensor comprises a substrate of a first conductivity type. First and second pixels are arrayed over the substrate. A potential barrier is formed in a region of the substrate corresponding to the first pixel but not in a region of the substrate corresponding to the second pixel. The second pixel is responsive to a color having a wavelength longer than the color to which the first pixel is responsive. The potential barrier is doped with dopants by a high energy ion implantation dopants or by an ion implantation or diffusion during epitaxial growth of the P-type epitaxial layer.

Abstract: A stratified photodiode for high resolution CMOS image sensors implemented with STI technology is provided. The photodiode includes a semi-conductive layer of a first conductivity type, multiple doping regions of a second conductivity type, multiple doping regions of the first conductivity type, and a pinning layer. The multiple doping regions of the second conductivity type are formed to different depths in the semi-conductive layer. The multiple doping regions of the first conductivity type are disposed between the multiple doping regions of the second conductivity type and form multiple junction capacitances without full depletion. In particular, the stratified doping arrangement allows the photodiode to have a small size, high charge storage capacity, low dark current, and low operation voltages.

Abstract: Provided is a solid-state CMOS image sensor, specifically a CMOS image sensor pixel that has stacked photo-sites, high sensitivity, and low dark current. In an image sensor including an array of pixels, each pixel includes: a standard photo-sensing and charge storage region formed in a first region under a surface portion of a substrate and collecting photo-generated carriers; a second charge storage region formed adjacent to the surface portion of the substrate and separated from the standard photo-sensing and charge storage region; and a potential barrier formed between the first region and a second region underneath the first region and diverting the photo-generated carriers from the second region to the second charge storage region.

Abstract: A back side illuminated image sensor may be provided with an array of image sensor pixels. Each pixel may include a substrate having a front surface and a back surface. The pixels may have a charge storage region at the back surface and a charge readout node at the front surface of the substrate. The pixels may receive light at the back surface. Photo-generated charge may be accumulated at the charge storage region during a charge integration cycle. Upon completion of the charge integration cycle, a transfer gate formed at the front surface may be pulsed high to move the charge from the charge storage region to the charge readout node using a global shutter algorithm. The pixels may include two reset transistors that are coupled to column feedback amplifier circuitry for mitigating kTC-reset noise when the pixels are operated in a global shutter mode.

Abstract: A back side illuminated image sensor may be provided with an array of image sensor pixels. Each image sensor pixel may include a substrate having a front surface and a back surface. The image sensor pixels may have a charge storage region formed at the back surface and a charge readout node formed at the front surface of the substrate. The image sensor pixels may receive image light at the back surface of the substrate. Photo-generated charge may be accumulated at the charge storage region during a charge integration cycle. Upon completion of the charge integration cycle, a transfer gate formed at the front surface may be pulsed high to move the charge from the charge storage region to the charge readout node. The charge may be converted to a voltage at the charge readout node and may be read out using a rolling shutter readout mode.

Abstract: The present invention relates to a junction gate photo-diode (JGP) pixel that includes a JGP for accumulating charge in response to impinging photons. The JGP is positioned on a substrate and includes a top n layer, a middle p layer and a bottom n layer forming a n-p-n junction, and a control terminal coupled to the top n layer. Also included is a floating diffusion (FD) positioned on the substrate and coupled to a pixel output line through an amplifier. Also included is a pinned barrier (PB) positioned on the substrate between the JGP and the FD, the PB temporarily blocks charge transfer between the JGP and the FD. The accumulated charge is transferred from the JGP to FD by applying a control voltage to the JGP control terminal.

Abstract: An image sensor with an organic photoelectric film for converting light into charge may be provided. The image sensor may include an array of image sensor pixels. Each image sensor pixel may include a charge-integrating pinned diode that collects photo-generated charge from the photoelectric film during an integration period. An anode electrode may be coupled to an n+ doped charge injection region in the charge-integrating pinned diode and may be used to convey the photo-generated charge from the photoelectric film to the charge-integrating pinned diode. Upon completion of a charge integration cycle, a first transfer transistor gate may be pulsed to move the charge from the charge-integrating pinned diode to a charge-storage pinned diode. The charge may be transferred from the charge-storage pinned diode to a floating diffusion node for readout by pulsing a gate of a second charge transfer transistor.

Abstract: The present invention provides a junction gate photo-diode (JGP) pixel that includes a JGP accumulating charge in response to impinging photons. The JGP is positioned on a substrate and includes a top n layer, a middle p layer and a bottom n layer forming a n-p-n junction, and a control terminal coupled to the top n layer. Also includes is a floating diffusion (FD) positioned on the substrate and coupled to a pixel output line through an amplifier. Also includes is a pinned barrier (PB) and a storage gate (SG) positioned on the substrate between the JGP and the FD. The PB temporarily blocks charge transfer between the JGP and the FD, and the SG stores the accumulated charge from the JGP, and transfers the stored charge to the FD for readout.

Abstract: The invention describes in detail a solid-state CMOS image sensor, specifically the CMOS image sensor pixel that has only two row lines per pixel, pinned photodiode for sensing light, and one or two column lines. The pixel does not have an address transistor and the sensing and reset transistors are both MOS p-channel type. This architecture results in a low noise operation with a very small output transistor random noise. In addition this new pixel architecture allows for the standard CDS signal processing operation, which reduces the pixel to pixel non-uniformities and minimizes kTC reset noise. The pixel has high sensitivity, high conversion gain, high response uniformity, and low noise, which is enabled by the efficient 3T pixel layout.

Abstract: A pixel of an image sensor includes only two signal lines per pixel, a pinned photodiode for sensing light, a floating base bipolar transistor, and no reset and address transistors. The floating base bipolar transistor provides the pixel with a gain, which can increase pixel sensitivity and reduce noise. The pixel also incorporates a vertical blooming control structure for an efficient blooming suppression. The output terminals of the pixel are coupled to a common column output line terminated by a special current sensing correlated double sampling circuit, which is used for subtraction of emitter leakage current. Based on this structure, the pixel has high sensitivity, high response uniformity, low noise, reduced size, and efficient layout.