Abstract: Electronic devices may include High Dynamic Range (HDR) complementary metal-oxide-semiconductor (CMOS) image sensor arrays that are illuminated from the back side of the substrate and operate in a rolling shutter (RS) scanning mode. An image sensor may include stacked chips to improve image sensor performance. For example, by stacking photodiodes on top of each other and using dichroic dielectric layers in chip-to-chip isolation, sensor sensitivity may be increased, Moiré effect may be reduced, and the overall image sensor performance may be improved. Image sensors may include a charge sensing and charge storing scheme where charge generated by low incident light levels is transferred onto a charge sensing node of an in-pixel inverting feedback amplifier and charge generated by high incident light levels overflows a certain potential barrier built in the pixel, is stored on capacitors, and is sensed by a source follower.

Abstract: A CMOS image sensor may have back-side illuminated pixels and operate in a global shutter scanning mode. The CMOS image sensor may be implemented using three-layer chip stacking. The chip to chip electrical connections between the upper chip and the middle chip may be formed via hybrid bonding. Two bonding pads may be included in each pixel. The electrical connections between the middle chip and the lower chip may be formed at the periphery of the array. Using three-layer chip stacking with hybrid bonding allows for the transferring and storing of signals from the upper chip on the middle chip. A signal from low light level illumination and a charge overflow signal from high light level illumination may both be transferred to the middle chip. The image sensor may be able to use a global shutter scanning mode having high dynamic range.

Abstract: In electron multiplying charge coupled device (EMCCD) image sensors, electron traps in the dielectric stack underneath charge multiplication electrodes may cause undesirable gain ageing. To reduce the gain ageing drift effect, a dielectric stack may be formed that does not include electron traps in regions underneath charge multiplication electrodes. To accomplish this, silicon nitride in the dielectric stack may be removed in regions underneath the charge multiplication electrodes. The EMCCD image sensors can thus be fabricated with a stable charge carrier multiplication gain during their operational lifetime.

Abstract: An image sensor may be provided with an array of image sensor pixels formed on a substrate having front and back surfaces. Each pixel may have a photodiode that receives light through the back surface, a floating diffusion node, a charge transfer gate, and first and second reset transistor gates. A source follower transistor may have a gate coupled to the floating diffusion node and a source coupled to an addressing transistor. The pixel may be coupled to a column feedback amplifier through the addressing transistor and a column feedback reset path. The amplifier may provide a kTC-reset noise compensation voltage to the reset transistors for storage on a holding capacitor coupled between the floating diffusion and a drain terminal of the source follower. The floating diffusion may be bounded at the front surface by the transfer gate, the reset gate, and p-type doped regions.

Abstract: Various embodiments of the present technology may comprise a method and apparatus for an image sensor. The image sensor may be configured as a stacked image sensor with two or more chips stacked vertically. The image sensor may comprise a plurality of pixel circuits, wherein portions of the pixel circuit are arranged on separate chips. Each pixel circuit may comprise an amplifier with a first feedback network to increase the sensor sensitivity, to reduce noise in the pixel signal, and to reduce the voltage swing on the FD node. Each pixel circuit may further comprise a second feedback network to stabilize the common-mode voltage of the pixel signal amplifier.

Abstract: An image sensor may be provided with an array of image sensor pixels formed on a substrate having front and back surfaces. Each pixel may have a photodiode that receives light through the back surface, a floating diffusion node, a charge transfer gate, and first and second reset transistor gates. A source follower transistor may have a gate coupled to the floating diffusion node and a source coupled to an addressing transistor. The pixel may be coupled to a column feedback amplifier through the addressing transistor and a column feedback reset path. The amplifier may provide a kTC-reset noise compensation voltage to the reset transistors for storage on a holding capacitor coupled between the floating diffusion and a drain terminal of the source follower. The floating diffusion may be bounded at the front surface by the transfer gate, the reset gate, and p-type doped regions.

Abstract: An image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a charge storage region, and a charge overflow circuit. The charge storage region may be used to operate the image sensor array in global shutter mode. During high light level illumination, the charge overflow circuit may divert charge away from the photodiode such that only a predetermined portion of the accumulated charge remains in the photodiode. During low light level illumination all of the accumulated charge may be stored in the pixel photodiode. The charge overflow circuit may include a transistor and a resistor or capacitor. By implementing a charge overflow circuit, the size of the charge storage region may be reduced while still preserving the high dynamic range and low noise of the image sensor during all light illumination conditions.

Abstract: Imaging pixels may be operated in a rolling shutter scanning mode. Charge signal that is generated on a first chip may be capacitively coupled to signal processing circuits on a second chip. A capacitor may be placed in the signal path that provides signal coupling between the chips and stores overflow charge from pixels that have been exposed to high light level illumination. This enables high dynamic range using only a single charge integration time. The pixel may include an in-pixel negative feedback amplifier. The chip-to-chip electrical connections between the first and second chips may be realized at each pixel as a hybrid bond with a single bond per pixel. Image sensors fabricated using this technology may have small size pixels, high resolution, high dynamic range, and a single charge integration time.

Abstract: An image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a charge storage region, and a charge overflow circuit. The charge storage region may be used to operate the image sensor array in global shutter mode. During high light level illumination, the charge overflow circuit may divert charge away from the photodiode such that only a predetermined portion of the accumulated charge remains in the photodiode. During low light level illumination all of the accumulated charge may be stored in the pixel photodiode. The charge overflow circuit may include a transistor and a resistor or capacitor. By implementing a charge overflow circuit, the size of the charge storage region may be reduced while still preserving the high dynamic range and low noise of the image sensor during all light illumination conditions.

Abstract: In one form, a hybrid bonded image sensor comprises a photodiode chip, a circuit carrying chip, and an interconnection. The photodiode chip provides charge to a first floating diffusion in response to incident light, wherein the first floating diffusion is coupled to a first terminal on a first surface of the photodiode chip. The circuit carrying chip has a first terminal aligned with the first terminal of the photodiode chip, the circuit carrying chip forming an output voltage based on charge transferred on the first floating diffusion sensed from the first terminal thereof. The interconnection connects the first terminal of the photodiode chip to the first terminal of the circuit carrying chip.

Abstract: A CMOS image sensor may have back-side illuminated pixels and operate in a global shutter scanning mode. The CMOS image sensor may be implemented using three-layer chip stacking. The chip to chip electrical connections between the upper chip and the middle chip may be formed via hybrid bonding. Two bonding pads may be included in each pixel. The electrical connections between the middle chip and the lower chip may be formed at the periphery of the array. Using three-layer chip stacking with hybrid bonding allows for the transferring and storing of signals from the upper chip on the middle chip. A signal from low light level illumination and a charge overflow signal from high light level illumination may both be transferred to the middle chip. The image sensor may be able to use a global shutter scanning mode having high dynamic range.

Abstract: An image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a floating diffusion node, and a charge transferring transistor. The charge transferring transistor may be a dual gate transistor having first and second gate terminals. A suitable bias may be applied to the second gate terminal to alter the capacitance of the floating diffusion node. The amount of electrons that may be accommodated by the floating diffusion node may be altered with application of a varying voltage level bias at the second gate terminal. By implementing a dual gate transistor, dynamic range compression and anti-blooming charge overflow may be implemented directly in the pixel to reduce image sensor pixel size and cost.

Abstract: An image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a charge storage region, and a charge overflow circuit. The charge storage region may be used to operate the image sensor array in global shutter mode. During high light level illumination, the charge overflow circuit may divert charge away from the photodiode such that only a predetermined portion of the accumulated charge remains in the photodiode. During low light level illumination all of the accumulated charge may be stored in the pixel photodiode. The charge overflow circuit may include a transistor and a resistor or capacitor. By implementing a charge overflow circuit, the size of the charge storage region may be reduced while still preserving the high dynamic range and low noise of the image sensor during all light illumination conditions.

Abstract: An image sensor with an organic photoelectric film for converting light into charge may be provided. The image sensor may include an array of image sensor pixels. Each image sensor pixel may include a charge-integrating pinned diode that collects photo-generated charge from the photoelectric film during an integration period. An anode electrode may be coupled to an n+ doped charge injection region in the charge-integrating pinned diode and may be used to convey the photo-generated charge from the photoelectric film to the charge-integrating pinned diode. Upon completion of a charge integration cycle, a first transfer transistor gate may be pulsed to move the charge from the charge-integrating pinned diode to a charge-storage pinned diode. The charge may be transferred from the charge-storage pinned diode to a floating diffusion node for readout by pulsing a gate of a second charge transfer transistor.

Abstract: An image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a floating diffusion node, and charge transfer gate. An amplifying transistor may have a gate terminal coupled to the floating diffusion and a drain terminal coupled to an output node. The amplifying transistor may provide signal corresponding to transferred charge with a greater than unity voltage gain. A negative voltage feedback capacitor having variable capacitance may be coupled between the output node and the floating diffusion node thereby increasing the pixel dynamic range. A reset transistor may be coupled between the floating diffusion and output node. The amplifying transistor may include a p-channel transistor formed within a mini n-well region of the pixel or an n-channel transistor formed within a mini p-well region. The pixel may have increased storage capacity and dynamic range relative to conventional designs.

Abstract: A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer disposed on the backside passivation layer.

Abstract: An image sensor having small pixels with high charge storage capacity, low dark current, no image lag, and good blooming control may be provided. The high charge storage capacity is achieved by placing a p+ type doped layer under the pixel charge storage region with an opening in it for allowing photo-generated charge carriers to flow from the silicon hulk to the charge storage well located near the surface of the photodiode. A compensating n-type doped implant may be formed in the opening. Image lag is prevented by placing a p? type doped region under the p+ type doped photodiode pinning layer and aligned with the opening. Blooming control is achieved by adjusting the length of the transfer gate in the pixel and thereby adjusting the punch-through potential under the gate.

Abstract: An image sensor may be provided with an array of image pixels formed on a substrate having front and back surfaces. Each pixel may have a photodiode that receives light through the back surface, a floating diffusion node, and a charge transfer gate. The floating diffusion node may be formed in the center of the photodiode and may be surrounded by the charge transfer gate at the front surface. The charge transfer gate may isolate the floating diffusion node from the surrounding photodiode. The pixel may include reset transistor gates, an addressing transistor gate, and a source follower transistor arranged about the periphery of the photodiode. By centering the floating diffusion node and charge transfer gate within the photodiode, the image pixels may have improved shutter efficiency and charge transfer efficiency relative to pixels having floating diffusion nodes at non-centralized locations.

Abstract: An image sensor may include an array of pixels that do not include any source follower, reset, or addressing transistors, which helps to increase pixel well capacity, reduces or eliminates random telegraph signal (RTS) noise, and reduces undesirable dark current. Charge to voltage conversion may be performed by charge detection circuitry that is external to the array of pixels. The charge detection circuitry may include amplifier circuitry such as an operational amplifier and may be located at the periphery of the array of pixels or on a different semiconductor substrate. By locating the charge detection circuitry outside of the array of pixels, additional flexibility may be provided for the charge detection circuitry. The charge detection circuitry may be provided with switchable gain or with non-linear charge to voltage conversion capability.

Abstract: An image sensor may include image sensor pixels formed on a substrate. Each pixel may have a photodiode, a floating diffusion node, and charge transfer gate. The pixel may include an n-type doped well region and a p-channel MOS source follower transistor formed within the n-well region. An n-channel MOS reset transistor may be coupled between the floating diffusion region and a bias voltage column line and may have a drain terminal that overlaps with the n-well region. If desired, the pixel may include a p-channel JFET source follower transistor formed within the floating diffusion region on the substrate and an n-channel MOSFET reset transistor coupled to the floating diffusion. The polarities of the doping in the substrate on which the pixels are formed may be reversed. The pixel may be formed without row select transistors to increase photodiode area and charge storage capacity.