Abstract: Operations for integrating thermoelectric devices in Fin FET technology may be implemented in a semiconductor device having a thermoelectric device. The thermoelectric device includes a substrate and a fin structure disposed on the substrate. The thermoelectric device includes a first connecting layer and a second connecting layer disposed on opposing ends of the fin structure. The thermoelectric device includes a first thermal conductive structure thermally and a second thermal conductive structure thermally coupled to the opposing ends of the fin structure. The fin structure may be configured to transfer heat from one of the first thermal conductive structure or the second thermal conductive structure to the other thermal conductive structure based on a direction of current flow through the fin structure. In this regard, the current flow may be adjusted by a power circuit electrically coupled to the thermoelectric device.

Abstract: A method of making a semiconductor device includes defining a first fin structure over a major surface of a substrate, wherein the first fin includes a first material. The method includes defining a second fin structure over the major surface of the substrate. Defining the second fin structure includes forming a lower portion of the second fin structure, closest to the substrate, having the first material, and forming an upper portion of the second fin structure, farthest from the substrate, having a second material different from the first material. The method includes forming a dielectric material over the substrate and between the first and second fin structures. The method includes removing the upper portion of the second fin structure, wherein removing the upper portion of the second fin structure includes reducing a height of the second fin structure to be less than a height of the first fin structure.

Abstract: Operations for integrating thermoelectric devices in Fin FET technology may be implemented in a semiconductor device having a thermoelectric device. The thermoelectric device includes a substrate and a fin structure disposed on the substrate. The thermoelectric device includes a first connecting layer and a second connecting layer disposed on opposing ends of the fin structure. The thermoelectric device includes a first thermal conductive structure thermally and a second thermal conductive structure thermally coupled to the opposing ends of the fin structure. The fin structure may be configured to transfer heat from one of the first thermal conductive structure or the second thermal conductive structure to the other thermal conductive structure based on a direction of current flow through the fin structure. In this regard, the current flow may be adjusted by a power circuit electrically coupled to the thermoelectric device.

Abstract: Operations for integrating thermoelectric devices in Fin FET technology may be implemented in a semiconductor device having a thermoelectric device. The thermoelectric device includes a substrate and a fin structure disposed on the substrate. The thermoelectric device includes a first connecting layer and a second connecting layer disposed on opposing ends of the fin structure. The thermoelectric device includes a first thermal conductive structure thermally and a second thermal conductive structure thermally coupled to the opposing ends of the fin structure. The fin structure may be configured to transfer heat from one of the first thermal conductive structure or the second thermal conductive structure to the other thermal conductive structure based on a direction of current flow through the fin structure. In this regard, the current flow may be adjusted by a power circuit electrically coupled to the thermoelectric device.

Abstract: A semiconductor device includes a substrate having a major surface. The semiconductor device includes a dielectric material having a uniform thickness on the major surface of the substrate. The semiconductor device includes a first plurality of fins extending from the major surface of the substrate, wherein each fin of the first plurality of fins has a first height from the major surface of the substrate. The semiconductor device includes a second plurality of fins extending from the major surface of the substrate, wherein a first fin of the second plurality of fins is on a first side of the first plurality of fins, a second fin of the second plurality of fins is on a second side of the first plurality of fins opposite the first side, each fin of the second plurality of fins has a second height different from the first height.

Abstract: A semiconductor device including a substrate having a major surface. The semiconductor device further includes a dielectric material on the major surface of the substrate. The semiconductor device further includes a first plurality of fins extending from the major surface of the substrate, wherein the dielectric material surrounding each fin of the first plurality of fins has a first thickness. The semiconductor device further includes a second plurality of fins extending from the major surface of the substrate, wherein a first fin of the second plurality of fins is on a first side of the first plurality of fins, a second fin of the second plurality of fins is on a second side of the first plurality of fins opposite the first side, the dielectric material surround each fin of the second plurality of fins has a second thickness, and the second thickness is different from the first thickness.

Abstract: A method of making a semiconductor device includes defining a first fin structure over a major surface of a substrate, wherein the first fin includes a first material. The method includes defining a second fin structure over the major surface of the substrate. Defining the second fin structure includes forming a lower portion of the second fin structure, closest to the substrate, having the first material, and forming an upper portion of the second fin structure, farthest from the substrate, having a second material different from the first material. The method includes forming a dielectric material over the substrate and between the first and second fin structures. The method includes removing the upper portion of the second fin structure, wherein removing the upper portion of the second fin structure includes reducing a height of the second fin structure to be less than a height of the first fin structure.

Abstract: A method includes identifying fingers of a first device and fingers of a second device. The method includes grouping the fingers of the first device into a first finger group and a second finger group, wherein the first finger group is electrically connected to the second finger group. The method further includes positioning the first finger group extends across a first doped region. The method further includes positioning the second finger group extends across a second doped region, wherein the second doped region has a same dopant type as the first doped region. The method further includes grouping the fingers of the second device into a third finger group and a fourth finger group, wherein the third finger group is electrically connected to the fourth finger group. The method further includes positioning the third finger group and the fourth finger group extending across the second doped region.

Abstract: A method of manufacturing a semiconductor device includes implanting a channel region of a first transistor and a channel region of a second transistor to have a first conductivity type. The method further includes forming source/drain regions of the first transistor to have the first conductivity type and source/drain regions of the second transistor to have a second conductivity type, wherein the second conductivity is different from the first conductivity type. The method further includes depositing a first work function layer over the channel region of the first transistor. The method further includes depositing a second work function layer over the channel region of the second transistor, wherein the first work function layer includes a same material as the second work function layer.

Abstract: A semiconductor device includes a substrate, a first transistor on the substrate, and a second transistor on the substrate. The first transistor has a first threshold voltage, and a channel region and source/drain regions of the first transistor are N-type. The second transistor has a second threshold voltage, a channel region of the second transistor is N-type and source/drain regions of the second transistor are P-type, and an absolute value of the first threshold voltage is substantially equal to an absolute value of the second threshold voltage.

Abstract: A method includes identifying fingers of a first device and fingers of a second device. The method includes grouping the fingers of the first device into a first finger group and a second finger group, wherein the first finger group is electrically connected to the second finger group. The method further includes positioning the first finger group extends across a first doped region. The method further includes positioning the second finger group extends across a second doped region, wherein the second doped region has a same dopant type as the first doped region. The method further includes grouping the fingers of the second device into a third finger group and a fourth finger group, wherein the third finger group is electrically connected to the fourth finger group. The method further includes positioning the third finger group and the fourth finger group extending across the second doped region.

Abstract: A circuit layout includes a first device having a first set of fingers, wherein the first set of fingers is separated into a first finger group and a second finger group, the first finger group comprising a first number of fingers, and the second finger group comprising a second number of fingers. The circuit layout further includes a second device having a second set of fingers, wherein the second set of fingers includes a third finger group having a third number of fingers. The first finger group, the second finger group and the third finger group extend across a first doped region, and the third finger group is between the first finger group and the second finger group.

Abstract: A semiconductor device including a substrate having a major surface. The semiconductor device further includes a dielectric material on the major surface of the substrate. The semiconductor device further includes a first plurality of fins extending from the major surface of the substrate, wherein the dielectric material surrounding each fin of the first plurality of fins has a first thickness. The semiconductor device further includes a second plurality of fins extending from the major surface of the substrate, wherein a first fin of the second plurality of fins is on a first side of the first plurality of fins, a second fin of the second plurality of fins is on a second side of the first plurality of fins opposite the first side, the dielectric material surround each fin of the second plurality of fins has a second thickness, and the second thickness is different from the first thickness.

Abstract: A semiconductor apparatus including a substrate having a substrate major surface, a dielectric material on the substrate major surface and having a second major surface distanced from the substrate major surface, and a plurality of fins extending from the substrate major surface through the dielectric material where the plurality of fins includes a first subset of fins and a second subset of fins, the first subset of fins located closer to a center of the plurality of fins than the second subset of fins, and an amount of heat generated during operation of the semiconductor device by each fin of the first subset of fins is less than an amount of heat generated by each fin of the second subset of fins during operation of the semiconductor device.

Abstract: A semiconductor device includes a substrate, a first transistor on the substrate, and a second transistor on the substrate. The first transistor has a first threshold voltage, and a channel region and source/drain regions of the first transistor are N-type. The second transistor has a second threshold voltage, a channel region of the second transistor is N-type and source/drain regions of the second transistor are P-type, and an absolute value of the first threshold voltage is substantially equal to an absolute value of the second threshold voltage.

Abstract: An integrated circuit (IC) and a method for operating the IC are provided. The IC comprises a device under test and a first heater. The first heater is located at a first side of the device and provides heat to control a temperature of the device. The first heater comprises a semiconductor device having a first doped region and a second doped region having a conductivity type opposite to that of the first doped region, the first doped region interfacing with the second doped region.

Abstract: A semiconductor apparatus including a substrate having a substrate major surface, a dielectric material on the substrate major surface and having a second major surface distanced from the substrate major surface, and a plurality of fins extending from the substrate major surface through the dielectric material where the plurality of fins includes a first subset of fins and a second subset of fins, the first subset of fins located closer to a center of the plurality of fins than the second subset of fins, and an amount of heat generated during operation of the semiconductor device by each fin of the first subset of fins is less than an amount of heat generated by each fin of the second subset of fins during operation of the semiconductor device.

Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.

Abstract: A transistor includes source region and drain regions, a channel region, a drift region, a gate, a dummy gate, a gate dielectric layer and an interconnection line. The source and drain regions of a first conductivity type are in a substrate. The channel region of a second conductivity type is in the substrate and surrounds the source region. The drift region of the first conductivity type is beneath the drain region and extends toward the channel region. The gate is over the substrate and overlapped with the channel region and the drift region. The dummy gate is over the drift region and laterally adjacent to the gate. The gate dielectric layer is between the gate and the substrate and between the dummy gate and the drift region. The interconnection line is electrically connected to the dummy gate and configured to provide a voltage potential thereto.

Abstract: An integrated circuit (IC) and a method for operating the IC are provided. The IC comprises a device under test and a first heater. The first heater is located at a first side of the device and provides heat to control a temperature of the device. The first heater comprises a semiconductor device having a first doped region and a second doped region having a conductivity type opposite to that of the first doped region, the first doped region interfacing with the second doped region.