Patents by Inventor Jiaw Ren Shih
Jiaw Ren Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030102485Abstract: A silicon controlled rectifier includes a pair of complementary bipolar transistors. At least one of the pair of transistors exhibits a reach-through effect that occurs prior to the avalanche junction voltage breakdown.Type: ApplicationFiled: December 4, 2001Publication date: June 5, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shui-Hung Chen, Jian-Hsing Lee, Jiaw-Ren Shih
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Patent number: 6541824Abstract: An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors.Type: GrantFiled: September 21, 2001Date of Patent: April 1, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jian-Hsing Lee, Jiaw-Ren Shih, Shui-Hung Chen, Yi-Hsun Wu
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Publication number: 20020164848Abstract: CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively.Type: ApplicationFiled: May 16, 2002Publication date: November 7, 2002Inventors: Jian-Hsing Lee, Jiaw-Ren Shih, Shui-Hung Chen, Ping-Lung Liao
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Patent number: 6459127Abstract: NMOS transistors for a high voltage process are protected from electrostatic discharge (ESD) by parasitic SCRs, where the two NMOS transistors and the two SCRs are designed to be in a completely symmetrical arrangement so that the currents in the components of the SCRs are completely uniform. This symmetry is achieved by adding a p+ diffusion to the source of one of the NMOS transistors. The added p+ diffusion guarantees that the resistance seen by both SCRs is identical. This insures even current distribution between both SCRs and thereby improves the high voltage characteristics of the ESD device.Type: GrantFiled: January 14, 2002Date of Patent: October 1, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jian-Hsing Lee, Kuo-Chio Liu, Bing-Lung Liao, Jiaw-Ren Shih
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Patent number: 6441438Abstract: An ESD protection structure that when connected between an input/output pad on a semiconductor substrate and a reference voltage source, will protect internal circuits formed on the semiconductor substrate from over stress due to excessively high voltages of an ESD voltage source. The ESD protection structure has a uniform discharge current to prevent damage to the ESD protection device thus allowing increased protection to the internal circuits. The ESD protection device has at least one source region that is the emitters of parasitic transistors connected to the reference voltage source and at least one drain region that is the collectors of the parasitic transistors connected to the junction of the input/output pad and the internal circuitry. The ESD protection device further has at least one gate electrode formed above a channel region. The channel region is the region is between each of the source regions and the drain regions. The gate electrodes are connected to the reference voltage source.Type: GrantFiled: November 13, 2000Date of Patent: August 27, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jiaw-Ren Shih, Jian-Hsing Lee, Huey-Liang Hwang
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Patent number: 6437408Abstract: A plasma damage protection cell using floating N/P/N and P/N/P structure, and a method to form the same are disclosed. Floating structures of the protection cell and the floating gates for the MOS devices are formed simultaneously on a semiconductor substrate having shallow trench isolation. The floating structures are implanted separately to form the N/P/N and P/N/P bipolar base, emitter and collector regions while the source/drain of the respective NMOS and PMOS devices are implanted with appropriate sequencing. The floating structures are connected to the substrate with appropriate polarity to provide protection at low leakage current levels and with tunable punch-through voltages.Type: GrantFiled: July 13, 2001Date of Patent: August 20, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jiaw-Ren Shih, Shui-Hung Shen, Jian-Hsing Lee, Chrong Jung Lin
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Patent number: 6426855Abstract: A voltage clamping circuit that protects integrated circuits having multiple separate power supply voltage terminals from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage terminals. The voltage clamping circuit has two subgroups of Darlington connected clamping transistors. The first subgroup of Darlington connected clamping transistors is connected between the first power supply voltage terminal and the second power supply voltage terminal. If the differential voltage exceeds the first clamping voltage level, the first subgroup of Darlington connected clamping transistors turn on and restore the first differential voltage to a level less than the first clamping voltage level. The second subgroup of Darlington connected clamping transistors connected between the second power supply terminal and the first power supply terminal.Type: GrantFiled: June 18, 2001Date of Patent: July 30, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jian-Hsing Lee, Jiaw-Ren Shih, Yi-Hsun Wu, Jing-Meng Liu
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Patent number: 6420221Abstract: CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively.Type: GrantFiled: February 22, 2000Date of Patent: July 16, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jian-Hsing Lee, Jiaw-Ren Shih, Shui-hung Chen, Ping-Lung Liao
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Publication number: 20020081783Abstract: NMOS transistors for a high voltage process are protected from electrostatic discharge (ESD) by parasitic SCRs, where the two NMOS transistors and the two SCRs are designed to be in a completely symmetrical arrangement so that the currents in the components of the SCRs are completely uniform. This symmetry is achieved by adding a p+ diffusion to the source of one of the NMOS transistors. The added p+ diffusion guarantees that the resistance seen by both SCRs is identical. This insures even current distribution between both SCRs and thereby improves the high voltage characteristics of the ESD device.Type: ApplicationFiled: January 14, 2002Publication date: June 27, 2002Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Jian-Hsing Lee, Kuo-Chio Liu, Bing-Lung Liao, Jiaw-Ren Shih
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Patent number: 6362035Abstract: A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field isolation by a blanket boron ion implant over the whole wafer. The channel stop implant follows planarization of the field oxide and is thereby essentially at the same depth in both field and active regions. Subsequently implanted p- and n-wells are formed deeper than the channel stop layer, the n-well implant being of a sufficiently higher dose to over compensate the channel stop layer, thereby removing it's effect from the n-well. A portion of the channel stop implant under the field oxide adjacent the p-well provides effective anti-punchthrough protection with only a small increase in junction capacitance. The method is shown for, and is particularly effective in, processes utilizing shallow trench isolation.Type: GrantFiled: February 7, 2000Date of Patent: March 26, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jiaw-Ren Shih, Shui-Hung Chen, Jian-Hsing Lee, Hsien-Chin Lin
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Patent number: 6358781Abstract: NMOS transistors for a high voltage process are protected from electrostatic discharge (ESD) by parasitic SCRs, where the two NMOS transistors and the two SCRs are designed to be in a completely symmetrical arrangement so that the currents in the components of the SCRs are completely uniform. This symmetry is achieved by adding a p+ diffusion to the source of one of the NMOS transistors. The added p+ diffusion guarantees that the resistance seen by both SCRs is identical. This insures even current distribution between both SCRs and thereby improves the high voltage characteristics of the ESD device.Type: GrantFiled: June 30, 2000Date of Patent: March 19, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jian-Hsing Lee, Kuo-Chio Liu, Bing-Lung Liao, Jiaw-Ren Shih
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Publication number: 20020014665Abstract: An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors.Type: ApplicationFiled: September 21, 2001Publication date: February 7, 2002Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Jian-Hsing Lee, Jiaw-Ren Shih, Shui-Hung Chen, Yi-Hsun Wu
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Patent number: 6323523Abstract: An ESD protective circuit formed by n-type pull-up transistors and n-type pull-down transistors on a p-type silicon substrate for protecting an internal device circuit is disclosed. In the circuit, a n-well region having a p+ diffusion and a n+ diffusion therein being formed adjacent one drain region of one pull-up transistors, the p+ diffusion and a n+ diffusion, as well as all the drain regions of the pull-up transistors are coupled to a power supply. All the source regions of the pull-up transistors and drain regions of the pull-down transistors are connected to an I/O pad. All the source regions of the pull-down transistors including the p+ guardings are grounded. The gates of all transistors are connected to the internal device circuit so that the internal device circuit will be immunity from the ESD.Type: GrantFiled: January 31, 2000Date of Patent: November 27, 2001Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Hsing Lee, Yi-Hsun Wu, Shui-Hung Chen, Jiaw-Ren Shih
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Publication number: 20010036050Abstract: A voltage clamping circuit that protects integrated circuits having multiple separate power supply voltage terminals from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage terminals. The voltage clamping circuit has two subgroups of Darlington connected clamping transistors. The first subgroup of Darlington connected clamping transistors is connected between the first power supply voltage terminal and the second power supply voltage terminal. If the differential voltage exceeds the first clamping voltage level, the first subgroup of Darlington connected clamping transistors turn on and restore the first differential voltage to a level less than the first clamping voltage level. The second subgroup of Darlington connected clamping transistors connected between the second power supply terminal and the first power supply terminal.Type: ApplicationFiled: June 18, 2001Publication date: November 1, 2001Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Jian-Hsing Lee, Jiaw-Ren Shih, Yi-Hsun Wu, Jing-Meng Liu
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Patent number: 6306695Abstract: An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors.Type: GrantFiled: September 27, 1999Date of Patent: October 23, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jian-Hsing Lee, Jiaw-Ren Shih, Shui-Hung Chen, Yi-Hsun Wu
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Patent number: 6277723Abstract: A plasma damage protection cell using floating N/P/N and P/N/P structure, and a method to form the same are disclosed. Floating structures of the protection cell and the floating gates for the MOS devices are formed simultaneously on a semiconductor substrate having shallow trench isolation. The floating structures are implanted separately to form the N/P/N and P/N/P bipolar base, emitter and collector regions while the source/drain of the respective NMOS and PMOS devices are implanted with appropriate sequencing. The floating structures are connected to the substrate with appropriate polarity to provide protection at low leakage current levels and with tunable punch-through voltages.Type: GrantFiled: October 14, 1999Date of Patent: August 21, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jiaw-Ren Shih, Shui-Hung Chen, Jian-Hsing Lee, Chrong Jung Lin
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Patent number: 6271999Abstract: A voltage clamping circuit that protects integrated circuits having multiple separate power supply voltage terminals from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage terminals. The voltage clamping circuit has two subgroups of Darlington connected clamping transistors. The first subgroup of Darlington connected clamping transistors is connected between the first power supply voltage terminal and the second power supply voltage terminal. If the differential voltage exceeds the first clamping voltage level, the first subgroup of Darlington connected clamping transistors turn on and restore the first differential voltage to a level less than the first clamping voltage level. The second subgroup of Darlington connected clamping transistors connected between the second power supply terminal and the first power supply terminal.Type: GrantFiled: November 20, 1998Date of Patent: August 7, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jian-Hsing Lee, Jiaw-Ren Shih, Yi-Hsun Wu, Jing-Meng Liu
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Patent number: 6268992Abstract: Circuits, device structures and methods are disclosed which protect CMOS semiconductor devices, having oxides as thin as 32 Angstrom, from electrostatic discharge (ESD) by utilizing a parasitic silicon controlled rectifier (SCR), intrinsic to the semiconductor device. The protection is afforded by providing low voltage triggering of the parasitic SCR in the order of 1.2 Volt. Triggering at such low voltages is made possible by means of a displacement current trigger which causes components of the SCR (parasitic npn and pnp bipolar transistors) to conduct, i.e., to trigger the SCR. The displacement current is realized by a junction capacitance, which is connected on one side to the pad to be protected and on the other side to terminals of the aforementioned parasitic bipolar transistors. Two ways of realizing the junction capacitance are disclosed.Type: GrantFiled: April 15, 1999Date of Patent: July 31, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jian-Hsing Lee, Jiaw-Ren Shih, Yi-Hsun Wu, Jing-Meng Liu
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Patent number: 6258672Abstract: An ESD protection structure that when connected between an input/output pad on a semiconductor substrate and a reference voltage source, will protect internal circuits formed on the semiconductor substrate from over stress due to excessively high voltages of an ESD voltage source. The ESD protection structure has a uniform discharge current to prevent damage to the ESD protection device thus allowing increased protection to the internal circuits. The ESD protection device has at least one source region that is the emitters of parasitic transistors connected to the reference voltage source and at least one drain region that is the collectors of the parasitic transistors connected to the junction of the input/output pad and the internal circuitry. The ESD protection device further has at least one gate electrode formed above a channel region. The channel region is the region is between each of the source regions and the drain regions. The gate electrodes are connected to the reference voltage source.Type: GrantFiled: February 18, 1999Date of Patent: July 10, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jiaw-Ren Shih, Jian-Hsing Lee, Huey-Liang Hwang
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Patent number: 6249414Abstract: Circuits, device structures and methods are disclosed which protect CMOS semiconductor devices, having oxides as thin as 32 Angstrom, from electrostatic discharge (ESD) by utilizing a parasitic silicon controlled rectifier (SCR), intrinsic to the semiconductor device. The protection is afforded by providing low voltage triggering of the parasitic SCR in the order of 1.2 Volt. Triggering at such low voltages is made possible by means of a displacement current trigger which causes components of the SCR (parasitic npn and pnp bipolar transistors) to conduct, i.e., to trigger the SCR. The displacement current is realized by a junction capacitance, which is connected on one side to the pad to be protected and on the other side to terminals of the aforementioned parasitic bipolar transistors. Two ways of realizing the junction capacitance are disclosed.Type: GrantFiled: September 28, 2000Date of Patent: June 19, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jian-Hsing Lee, Jiaw-Ren Shih, Yi-Hsun Wu, Jing-Meng Liu