Patents by Inventor Jiaw Ren Shih
Jiaw Ren Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170012194Abstract: Operations for integrating thermoelectric devices in Fin FET technology may be implemented in a semiconductor device having a thermoelectric device. The thermoelectric device includes a substrate and a fin structure disposed on the substrate. The thermoelectric device includes a first connecting layer and a second connecting layer disposed on opposing ends of the fin structure. The thermoelectric device includes a first thermal conductive structure thermally and a second thermal conductive structure thermally coupled to the opposing ends of the fin structure. The fin structure may be configured to transfer heat from one of the first thermal conductive structure or the second thermal conductive structure to the other thermal conductive structure based on a direction of current flow through the fin structure. In this regard, the current flow may be adjusted by a power circuit electrically coupled to the thermoelectric device.Type: ApplicationFiled: July 7, 2015Publication date: January 12, 2017Inventors: Jhong-Sheng WANG, Jiaw-Ren SHIH, Hsiao-Hsuan HSU
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Publication number: 20160247913Abstract: A transistor includes source region and drain regions, a channel region, a drift region, a gate, a dummy gate, a gate dielectric layer and an interconnection line. The source and drain regions of a first conductivity type are in a substrate. The channel region of a second conductivity type is in the substrate and surrounds the source region. The drift region of the first conductivity type is beneath the drain region and extends toward the channel region. The gate is over the substrate and overlapped with the channel region and the drift region. The dummy gate is over the drift region and laterally adjacent to the gate. The gate dielectric layer is between the gate and the substrate and between the dummy gate and the drift region. The interconnection line is electrically connected to the dummy gate and configured to provide a voltage potential thereto.Type: ApplicationFiled: May 2, 2016Publication date: August 25, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jhong-Sheng WANG, Jiaw-Ren SHIH
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Patent number: 9373712Abstract: A transistor includes source region and drain regions, a channel region, a drift region, a gate, a dummy gate, a gate dielectric layer and an interconnection line. The source and drain regions of a first conductivity type are in a substrate. The channel region of a second conductivity type is in the substrate and surrounds the source region. The drift region of the first conductivity type is beneath the drain region and extends toward the channel region. The gate is over the substrate and overlapped with the channel region and the drift region. The dummy gate is over the drift region and laterally adjacent to the gate. The gate dielectric layer is between the gate and the substrate and between the dummy gate and the drift region. The interconnection line is electrically connected to the dummy gate and configured to provide a voltage potential thereto.Type: GrantFiled: September 29, 2014Date of Patent: June 21, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jhong-Sheng Wang, Jiaw-Ren Shih
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Publication number: 20160126232Abstract: A circuit layout includes a first device having a first set of fingers, wherein the first set of fingers is separated into a first finger group and a second finger group, the first finger group comprising a first number of fingers, and the second finger group comprising a second number of fingers. The circuit layout further includes a second device having a second set of fingers, wherein the second set of fingers includes a third finger group having a third number of fingers. The first finger group, the second finger group and the third finger group extend across a first doped region, and the third finger group is between the first finger group and the second finger group.Type: ApplicationFiled: October 29, 2014Publication date: May 5, 2016Inventors: Shou-En LIU, Chun-Wei CHANG, Bi-Ling LIN, Yung-Sheng TSAI, Jiaw-Ren SHIH
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Publication number: 20160093729Abstract: A transistor includes source region and drain regions, a channel region, a drift region, a gate, a dummy gate, a gate dielectric layer and an interconnection line. The source and drain regions of a first conductivity type are in a substrate. The channel region of a second conductivity type is in the substrate and surrounds the source region. The drift region of the first conductivity type is beneath the drain region and extends toward the channel region. The gate is over the substrate and overlapped with the channel region and the drift region. The dummy gate is over the drift region and laterally adjacent to the gate. The gate dielectric layer is between the gate and the substrate and between the dummy gate and the drift region. The interconnection line is electrically connected to the dummy gate and configured to provide a voltage potential thereto.Type: ApplicationFiled: September 29, 2014Publication date: March 31, 2016Inventors: Jhong-Sheng WANG, Jiaw-Ren SHIH
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Publication number: 20140145194Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.Type: ApplicationFiled: January 28, 2014Publication date: May 29, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bi-Ling Lin, Jian-Hong Lin, Ming-Hong Hsieh, Lee-Der Chen, Jiaw-Ren Shih, Chwei-Ching Chiu
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Patent number: 8648592Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.Type: GrantFiled: September 13, 2011Date of Patent: February 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bi-Ling Lin, Jian-Hong Lin, Ming-Hong Hsieh, Lee-Der Chen, Jiaw-Ren Shih, Chwei-Ching Chiu
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Publication number: 20130063175Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.Type: ApplicationFiled: September 13, 2011Publication date: March 14, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bi-Ling Lin, Jian-Hong Lin, Ming-Hong Hsieh, Lee-Der Chen, Jiaw-Ren Shih, Chwei-Ching Chiu
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Patent number: 8288822Abstract: An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.Type: GrantFiled: June 29, 2011Date of Patent: October 16, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiaw-Ren Shih, Jian-Hsing Lee
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Publication number: 20110254091Abstract: An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.Type: ApplicationFiled: June 29, 2011Publication date: October 20, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiaw-Ren Shih, Jian-Hsing Lee
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Patent number: 7994577Abstract: An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.Type: GrantFiled: July 18, 2008Date of Patent: August 9, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiaw-Ren Shih, Jian-Hsing Lee
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Patent number: 7759962Abstract: A method for performing a bias temperature instability test on a device includes performing a first stress on the device. After the first stress, a first measurement is performed to determine a first parameter of the device. After the first measurement, a second stress is performed on the device, wherein only the first parameter is measured between the first stress and the second stress. The method further includes performing a second measurement to determine a second parameter of the device after the second stress. The second parameter is different from the first parameter.Type: GrantFiled: October 16, 2008Date of Patent: July 20, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiaw-Ren Shih, Neeraj Kumar Jha, Rakesh Ranjan, Naresh Kumar Emani
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Publication number: 20100097091Abstract: A method for performing a bias temperature instability test on a device includes performing a first stress on the device. After the first stress, a first measurement is performed to determine a first parameter of the device. After the first measurement, a second stress is performed on the device, wherein only the first parameter is measured between the first stress and the second stress. The method further includes performing a second measurement to determine a second parameter of the device after the second stress. The second parameter is different from the first parameter.Type: ApplicationFiled: October 16, 2008Publication date: April 22, 2010Inventors: Jiaw-Ren Shih, Neeraj Kumar Jha, Rakesh Ranjan, Naresh Kumar Emani
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Publication number: 20100013016Abstract: An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.Type: ApplicationFiled: July 18, 2008Publication date: January 21, 2010Inventors: Jiaw-Ren Shih, Jian-Hsing Lee
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Patent number: 7518192Abstract: A semiconductor structure for electrostatic discharge protection is presented. The semiconductor structure comprises a grounded gate nMOS (GGNMOS) having a substrate, a gate electrode, a source region and a drain region. A plurality of contact plugs is formed on the source and drain side. A plurality of first level vias is electrically coupled to the GGNMOS and has a substantially asymmetrical layout in the source and drain regions. A second level via(s) re-routes the ESD current to the desired first level vias. The uniformity of the current flow in the GGNMOS is improved.Type: GrantFiled: November 10, 2004Date of Patent: April 14, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Feng Yu, Jian-Hsing Lee, Jiaw-Ren Shih, Fu Chin Yang
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Patent number: 7420793Abstract: A circuit system is disclosed for protecting a capacitor coupled between a voltage supply node and a complementary voltage supply node from an ESD. The circuit system includes at least one NMOS transistor having a drain coupled to the voltage supply node, a source and a gate together coupled to the complementary voltage supply node, and at least one diode chain having one or more diodes serially coupled between the voltage supply node and the complementary voltage supply node. During an ESD event, the diode chain and the NMOS transistor dissipate an ESD current from the voltage supply node to the complementary voltage supply node, thereby protecting the capacitor from ESD induced damages.Type: GrantFiled: January 12, 2006Date of Patent: September 2, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shao-Chang Huang, Jian-Hsing Lee, Yi-Hsun Wu, Jiaw-Ren Shih
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Publication number: 20080137244Abstract: An electrostatic discharge (ESD) protection circuit. The ESD protection circuit comprises a silicon controlled rectifier (SCR) device and a metal-oxide-semiconductor (MOS) triggering device. The SCR device has a cathode connected to a first fixed potential and an anode. The MOS triggering device has a gate and a source connected to the first fixed potential and a drain connected to the anode. In addition, the MOS triggering device is not physically disposed in the SCR device.Type: ApplicationFiled: December 12, 2006Publication date: June 12, 2008Inventors: Kuo-Feng Yo, Jian-Hsing Lee, Jiaw-Ren Shih, Fu-Chin Yang
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Patent number: 7309905Abstract: A system and method is disclosed for implementing a new bipolar-based silicon controlled rectifier (SCR) circuit for an electrostatic discharge (ESD) protection. The SCR circuit comprises a bipolar device to be formed on a semiconductor substrate. The bipolar device comprises at least an N-well for providing a high resistance and a P+ material to be used as a collector thereof for further providing a high resistance. At least an Nmoat guard ring and a Pmoat guard ring surround the bipolar device, wherein when an ESD event occurs, the high resistance provided by the N-well and the P+ material of the bipolar device increases a turn-on speed.Type: GrantFiled: February 25, 2005Date of Patent: December 18, 2007Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Kuo-Feng Yu, Jian-Hsing Lee, Jiaw-Ren Shih, Fu Chin Yang
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Publication number: 20070257323Abstract: A stacked contact structure includes a first contact plug of a first conductive material filling a first contact hole in a first dielectric layer, and a second contact plug of a second conductive material filling a second contact hole in a second dielectric layer. The second conductive material is different from the first conductive material, and the second conductive material has an electrical resistance lower than that of the first conductive material.Type: ApplicationFiled: May 5, 2006Publication date: November 8, 2007Inventors: Ren-Fen Tsui, Jiaw-Ren Shih
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Patent number: RE40138Abstract: A process for fabricating input/output, N channel, (I/O NMOS) devices, featuring an ion implanted nitrogen region, used to reduce hot carrier electron, (HEC), injection, has been developed. The process features implanting a nitorgen region, at the interface of an overlying silicon oxide layer, and an underlying lightly doped source/drain, (LDD), region. The implantation procedure can either be performed prior to, or after, the deposition of a silicon oxide liner layer, in both cases resulting in a desired nitrogen pile-up at the oxide-LDD interface, as well as resulting, in a more graded LDD profile. An increase in the time to fail, in regards to HCE injection, for these I/O NMOS devices, is realized, when compared to counterparts fabricated without the nitrogen implantation procedure.Type: GrantFiled: May 21, 2003Date of Patent: March 4, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mu-Chi Chiang, Hsien-Chin Lin, Jiaw-Ren Shih