Abstract: A method of manufacturing a on-chip temperature controller by co-implanting P-type and N-type ions into poly load resistors. The N and P type implant dose can be selected to create the desired cut-off temperature. First, a polysilicon layer 30 is formed on a first insulation layer 20. The polysilicon layer 30 is patterning to form a first poly-load resistor 30A and a second poly-load resistor 30B. The first and the second poly-load resistors are connected to a temperature sensor circuit 12. Both p-type and n-type impurity ions are implanted into the polysilicon layer 30. An insulating dielectric layer 40 is formed over the polysilicon layer 30 and the first insulating layer 20. The polysilicon layer is annealed. The contact openings 44 are formed through the ILD dielectric layer 40 exposing portions of the polysilicon layer 30. Contacts 50 to the polysilicon layer 30 thereby forming a first and second poly-load resistors which are used a temperature on-chip sensors.

Abstract: A process for fabricating input/output, N channel, (I/O NMOS) devices, featuring an ion implanted nitrogen region, used to reduce hot carrier electron, (HEC), injection, has been developed. The process features implanting a nitorgen region, at the interface of an overlying silicon oxide layer, and an underlying lightly doped source/drain, (LDD), region. The implantation procedure can either be performed prior to, or after, the deposition of a silicon oxide liner layer, in both cases resulting in a desired nitrogen pile-up at the oxide-LDD interface, as well as resulting, in a more graded LDD profile. An increase in the time to fail, in regards to HCE injection, for these I/O NMOS devices, is realized, when compared to counterparts fabricated without the nitrogen implantation procedure.

Abstract: A new method of suppressing short channel effect without increasing junction leakage and capacitance using a single self-aligning delta-channel implant is described. A pad oxide layer is formed over a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer and patterned to leave an opening where a gate electrode will be formed. Dielectric spacers are formed on the sidewalls of the opening wherein a portion of the substrate is not covered by the spacers within the opening. A single delta-channel implant is made into the semiconductor substrate using the silicon nitride layer and the dielectric spacers as a mask. This delta-channel implant suppresses short channel effect without increasing junction leakage and capacitance. The dielectric spacers are removed. A polysilicon layer is deposited over the silicon nitride layer and within the opening and polished to leave the polysilicon layer only within the opening.

Abstract: In short-channel MOSFET devices with gates constructed using conventional double-diffusing techniques, damage to the silicon substrate region near the gate structure causes hot carrier effects that degrade the device performance. The inventive process described minimizes damage to the silicon substrate in the region of the metal gate structure thereby providing a MOSFET device with superior hot carrier effect performance.

Abstract: A new method is provided for the creation of a Shallow Trench Isolation region. A layer of pad oxide is deposited on the surface of a substrate; a layer of nitride is deposited over the layer of pad oxide. The layers of pad oxide and nitride are patterned and etched over the region where the STI is to be formed, a trench is etched in the silicon for the STI region. A layer of TEOS, that serves as a buffer spacer oxide, is deposited over the surface of the layer of nitride thereby including the inside of the created trench. The layer of TEOS is etched removing the TEOS from the surface of the nitride and from the bottom of the trench but leaving a layer of TEOS in place along the sidewalls of the trench. The bottom of the trench is next etched after which the TEOS spacer buffer is removed from the sidewalls of the trench. The sidewalls of the trench now have a non-linear profile.

Abstract: The invention provides a gate pocket implantation and post-processing sequence that allows for the creation of a deep and narrow pocket implant without affecting gate threshold voltage and the integrity of the gate oxide layer.

Abstract: A method is disclosed to provide for more robust latchup-immune CMOS transistors by increasing the breakover voltage VBO, or trigger point, of the parasitic npn and pnp transistors present in CMOS structures. These goals have been achieved by adding a barrier layer to both the n-well and p-well of a twin-well CMOS structure, thus increasing the energy gap for electrons and holes of the parasitic npn and pnp transistor, respectively.

Abstract: A method to channel erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to channel erase a flash EEPROM cell begins by removing the charge from the floating gate of the flash EEPROM cell. The channel erasing consists of applying a relatively large clipped sinusoidal negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a moderately large positive voltage pulse to a first diffusion region. At the same time a ground reference potential is applied to the semiconductor substrate, while the drain, the source and a second diffusion well are allowed to float.

Abstract: Methods are disclosed for depositing an in situ polysilicon layer on the back of a semiconductor wafer to reduce the temperature at the edge of the wafer during rapid thermal annealing (RTA). The reduced temperature results in decreased boron penetration at the edge of the wafer and a more uniform silicide resistance and threshold voltage across the wafer.

Abstract: The structure includes a plurality of first ring shape structure formed on a semiconductor wafer to act as the gates of the MOS devices. The areas in the inner side of the first ring shape structures are drain regions. A plurality of source regions having second ring shape structures are formed around each sides the first ring shape structures. A p conductive type region is formed in the wafer adjacent to the source regions. A third ring shape structure is formed in the semiconductor wafer to surround the p+conductive type region for serving as a guard ring.

Abstract: An electrostatic discharge (ESD) protective circuit for reducing the electron-tunneling phenomena in NMOS devices. Several complementary metal oxide semiconductor (CMOS) devices act as an ESD protective circuit from being destroyed. The CMOS devices are connected to an internal circuit and a power line provide a bias voltage for the devices. The drains of the CMOS devices are connected to a pad to output a driving current. A NMOS device is connected between the internal circuit and the ESD protective circuit for protecting the NMOS devices in the circuit. As an ESD pulse is input into the ESD protective circuit, the NMOS device is then turned on by the pulse. Thus, positive charges on the gate of the NMOS devices in the ESD circuit is conducted into ground. Therefore, the NMOS device between the internal circuit and the ESD circuit can prevent the gate oxide of the NMOS device in the circuit from damage.

Abstract: A structure and method for fabricating an ESD device for FET transistors by forming a silicon germanium region 40 under a channel region 44 of a field effect transistor (FET). The silicon germanium region 40 comprises the base of a parasitic bipolar 200 transistor that increases the turn on speed. The method comprises:a) forming a gate dielectric layer 20 over a substrate 10;b) forming a gate 30 over the gate 30; the substrate having a channel region under the gate; the channel region extending from the surface of the substrate to a channel depth below the substrate surface;c) forming a silicon germanium region 40 under the channel region 44 using a tilt angle ion implant of Germanium ions;d) forming source and drain doped regions 50 70 adjacent to the channel region and the silicon germanium region whereby the silicon germanium region comprises a base of a parasitic bipolar transistor 40.

Abstract: An improved process and integrated-circuit having CMOS (NMOS and/or PMOS) devices formed on a substrate and a NMOS electro static discharge circuit formed in a P well on the substrate. The improvement includes an electro static discharge NMOS circuit having an undoped polysilicon gate electrode, and the NMOS FET devices having n-type doped gate electrodes. The undoped gate polysilicon electrode of the electro static discharge transistor increases the gate oxide breakdown voltage thus making the ESD transistor able to withstand a greater voltage discharge and therefore providing better protection to the product devices.

Abstract: A process for fabricating MOSFET devices, in which performance, as well as reliability enhancements, are included, has been developed. An LDD process, using first an ion implanted phosphorous step, to address hot carrier lifetime phenomena, followed by a arsenic ion implantation step, used to improve device performance, is described.

Abstract: An improved process and integrated-circuit having CMOS (NMOS and/or PMOS) devices formed on a substrate and a NMOS electro static discharge circuit formed in a P well on the substrate. The improvement includes an electro static discharge NMOS circuit having an undoped polysilicon gate electrode, and the NMOS FET devices having n-type doped gate electrodes. The undoped polysilicon gate electrode of the electro static discharge transistor increases the gate oxide breakdown voltage thus making the ESD transistor able to withstand a greater voltage discharge and therefore providing better protection to the product devices.