Patents by Inventor Jiaw Ren Shih
Jiaw Ren Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7247543Abstract: A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.Type: GrantFiled: March 4, 2005Date of Patent: July 24, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiaw-Ren Shih, Jian-Hsing Lee, Shui-Hung Chen
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Publication number: 20070159754Abstract: A circuit system is disclosed for protecting a capacitor coupled between a voltage supply node and a complementary voltage supply node from an ESD. The circuit system includes at least one NMOS transistor having a drain coupled to the voltage supply node, a source and a gate together coupled to the complementary voltage supply node, and at least one diode chain having one or more diodes serially coupled between the voltage supply node and the complementary voltage supply node. During an ESD event, the diode chain and the NMOS transistor dissipate an ESD current from the voltage supply node to the complementary voltage supply node, thereby protecting the capacitor from ESD induced damages.Type: ApplicationFiled: January 12, 2006Publication date: July 12, 2007Inventors: Shao-Chang Huang, Jian-Hsing Lee, Yi-Hsun Wu, Jiaw-Ren Shih
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Publication number: 20060234399Abstract: A method is disclosed for enhancing ESD protection of integrated circuit devices. The method entails placing a resistor between an I/O pad and an ESD protection device on a semiconductor chip so that one end of the resistor connects to pins on said I/O pad and the other end connects to the ESD protection device.Type: ApplicationFiled: April 15, 2005Publication date: October 19, 2006Inventors: Jiaw-Ren Shih, Jian-Hsing Lee
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Publication number: 20060192251Abstract: A system and method is disclosed for implementing a new bipolar-based silicon controlled rectifier (SCR) circuit for an electrostatic discharge (ESD) protection. The SCR circuit comprises a bipolar device to be formed on a semiconductor substrate. The bipolar device comprises at least an N-well for providing a high resistance and a P+ material to be used as a collector thereof for further providing a high resistance. At least an Nmoat guard ring and a Pmoat guard ring surround the bipolar device, wherein when an ESD event occurs, the high resistance provided by the N-well and the P+ material of the bipolar device increases a turn-on speed.Type: ApplicationFiled: February 25, 2005Publication date: August 31, 2006Inventors: Kuo-Feng Yu, Jian-Hsing Lee, Jiaw-Ren Shih, Fu Yang
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Publication number: 20060097330Abstract: A semiconductor structure for electrostatic discharge protection is presented. The semiconductor structure comprises a grounded gate nMOS (GGNMOS) having a substrate, a gate electrode, a source region and a drain region. A plurality of contact plugs is formed on the source and drain side. A plurality of first level vias is electrically coupled to the GGNMOS and has a substantially asymmetrical layout in the source and drain regions. A second level via(s) re-routes the ESD current to the desired first level vias. The uniformity of the current flow in the GGNMOS is improved.Type: ApplicationFiled: November 10, 2004Publication date: May 11, 2006Inventors: Kuo-Feng Yu, Jian-Hsing Lee, Jiaw-Ren Shih, Fu Yang
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Publication number: 20050212097Abstract: Improving charged device model (CDM) electrostatic discharge (ESD) testing failure rate is disclosed by applying a capacitive coating to an integrated circuit (IC). The IC includes a primary substrate, a number of contacts, and the coating. The substrate has a top surface, a bottom surface, and side surfaces. The contacts are on the top surface, and are connectable to packaging element pins. The capacitive coating is on at least the bottom surface, to make contact with a lead frame intended to secure the substrate to the packaging element. The coating provides a capacitance electrically in series with the capacitance of the IC. The total capacitance during CDM testing is decreased, decreasing the RC constant governing discharge of charge placed on the IC. Discharge occurs more slowly, the discharge current being inversely related to the constant. The maximum discharge current is decreased, allowing the IC to better withstand CDM testing.Type: ApplicationFiled: March 29, 2004Publication date: September 29, 2005Inventors: Jiaw-Ren Shih, Jian-Hsing Lee
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Patent number: 6949802Abstract: The invention describes structures and a process for providing ESD protection between multiple power supply lines or buses on an integrated circuit chip. Special diode strings are used for the protection devices whereby the diodes are constructed across the boundary of an N-well and P substrate or P-well. The unique design provides very low leakage characteristics during normal circuit operation, as well as improved trigger voltage control achieved by stacking 2 or more diodes in a series string between the power buses.Type: GrantFiled: November 20, 2003Date of Patent: September 27, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jiaw-Ren Shih, Jian-Hsing Lee
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Patent number: 6937457Abstract: A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.Type: GrantFiled: October 27, 2003Date of Patent: August 30, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiaw-Ren Shih, Jian-Hsing Lee, Shui-Hung Chen
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Publication number: 20050176195Abstract: A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.Type: ApplicationFiled: March 4, 2005Publication date: August 11, 2005Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiaw-Ren Shih, Jian-Hsing Lee, Shui-Hung Chen
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Publication number: 20050110095Abstract: The invention describes structures and a process for providing ESD protection between multiple power supply lines or buses on an integrated circuit chip. Special diode strings are used for the protection devices whereby the diodes are constructed across the boundary of an N-well and P substrate or P-well. The unique design provides very low leakage characteristics during normal circuit operation, as well as improved trigger voltage control achieved by stacking 2 or more diodes in a series string between the power buses.Type: ApplicationFiled: November 20, 2003Publication date: May 26, 2005Inventors: Jiaw-Ren Shih, Jian-Hsing Lee
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Patent number: 6888248Abstract: A multi-level metal interconnect structure and method for forming the same for improving a resistance of CMOS transistors to electrostatic discharge (ESD) transient events is disclosed. A semiconductor device including at least one NMOS transistor electrically connected along at least one circuit pathway to an input/output signal source and a reference voltage potential; and, electrically connecting at least the input/output signal source to the at least one NMOS transistor with a metal interconnect line extended in length by compacting at least a portion of the metal interconnect line length portion into a serpentine shape within a predetermined volume of the semiconductor device.Type: GrantFiled: March 26, 2003Date of Patent: May 3, 2005Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Shui-Hung Chen, Jian-Hsing Lee, Jiaw-Ren Shih
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Publication number: 20050088801Abstract: A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.Type: ApplicationFiled: October 27, 2003Publication date: April 28, 2005Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jiaw-Ren Shih, Jian-Hsing Lee, Shui-Hung Chen
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Publication number: 20040188841Abstract: A multi-level metal interconnect structure and method for forming the same for improving a resistance of CMOS transistors to electrostatic discharge (ESD) transient events is disclosed. A semiconductor device including at least one NMOS transistor electrically connected along at least one circuit pathway to an input/output signal source and a reference voltage potential; and, electrically connecting at least the input/output signal source to the at least one NMOS transistor with a metal interconnect line extended in length by compacting at least a portion of the metal interconnect line length portion into a serpentine shape within a predetermined volume of the semiconductor device.Type: ApplicationFiled: March 26, 2003Publication date: September 30, 2004Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shui-Hung Chen, Jian-Hsing Lee, Jiaw-Ren Shih
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Patent number: 6762439Abstract: A new electrostatic discharge protection device is achieved. A p-well region is in a semiconductor substrate. An n+ region in the p-well region is connected to a first voltage supply. An n-well region in the p-well region is spaced from the n+ region such that a depletion region will extend therebetween during normal operation. A p+ region in the n-well region is connected to a second voltage supply of greater value than the first voltage supply during normal operation. Current is conducted through the n+ region to the p+ region during an electrostatic discharge event.Type: GrantFiled: July 5, 2001Date of Patent: July 13, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Shui-Hung Chen, Jian-Hsing Lee, Jiaw-Ren Shih, Ta-Lee Yu
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Patent number: 6747857Abstract: A novel device and process is described for an ESD protection device for complimentary cascaded NMOS output circuit strings. The invention consists of a clamping NMOS with gate connected to the input or output pad through a diode and connected to ground through a resistor. The clamping device drain is connected to the signal gate of the active output NMOS and the clamping device source is connected to ground. An ESD event causes the diode to go into breakdown mode and the conduction current across the resistor places a positive voltage on the clamping device gate turning the clamping device on. This clamps the active NMOS signal gate to ground assuring that the output NMOS remains in an off condition during the ESD event. This prevents any damage due to high current flow through the active, or used output inverter string.Type: GrantFiled: February 1, 2002Date of Patent: June 8, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jian-Hsing Lee, Hung-Der Su, Jiaw-Ren Shih
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Patent number: 6740934Abstract: Disclosed are structures and a method to increase the power dissipation of an output pad of an integrated circuit during electrostatic discharge (ESD) by preventing ESD current from flowing through resistive means between that output pad and an internal circuit. By splitting the active region and thereby creating a bipolar transistor which connects directly to the output pad, the resistive means is shunted when the bipolar transistor together with an already existing parasitic bipolar transistor conduct during ESD. Current flow in the resistive means is therefore eliminated and with it damaging power dissipation.Type: GrantFiled: June 3, 2003Date of Patent: May 25, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jian-Hsing Lee, Shui-Hun Chen, Jiaw-Ren Shih
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Publication number: 20030213999Abstract: Disclosed are structures and a method to increase the power dissipation of an output pad of an integrated circuit during electrostatic discharge (ESD) by preventing ESD current from flowing through resistive means between that output pad and an internal circuit. By splitting the active region and thereby creating a bipolar transistor which connects directly to the output pad, the resistive means is shunted when the bipolar transistor together with an already existing parasitic bipolar transistor conduct during ESD. Current flow in the resistive means is therefore eliminated and with it damaging power dissipation.Type: ApplicationFiled: June 3, 2003Publication date: November 20, 2003Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Jian-Hsing Lee, Shui-Hun Chen, Jiaw-Ren Shih
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Patent number: 6614693Abstract: A combination erase method to erase data from a flash EEPROM eliminates electrical charges trapped in the tunneling oxide of a flash EEPROM to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. A first embodiment method to erase a flash EEPROM cell begins by negative gate erasing to remove charges from the floating gate, followed by a source erasing to further remove charges from the floating gate, and finally followed by a channel erasing to detrap charges. A second embodiment begins with a negative gate erasing having a incremental stepping of the voltages to remove the charges from the floating gate. This followed by a source erasing to detrap the tunneling oxide of the EEPROM cell. A third embodiment begins with a source erasing having a incremental stepping of the voltages to remove the charges from the floating gate. This followed by a channel erasing to detrap the tunneling oxide of the EEPROM cell.Type: GrantFiled: March 19, 2002Date of Patent: September 2, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jian-Hsing Lee, Kuo-Reay Peng, Shui-Hung Chen, Jiaw-Ren Shih
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Patent number: 6614078Abstract: CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively.Type: GrantFiled: May 16, 2002Date of Patent: September 2, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jian-Hsing Lee, Jiaw-Ren Shih, Shui-Hung Chen, Ping-Lung Liao
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Patent number: 6582997Abstract: Disclosed are structures and a method to increase the power dissipation of an output pad of an integrated circuit during electrostatic discharge (ESD) by preventing ESD current from flowing through resistive means between that output pad and an internal circuit. By splitting the active region and thereby creating a bipolar transistor which connects directly to the output pad, the resistive means is shunted when the bipolar transistor together with an already existing parasitic bipolar transistor conduct during ESD. Current flow in the resistive means is therefore eliminated and with it damaging power dissipation.Type: GrantFiled: May 17, 2002Date of Patent: June 24, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jian-Hsing Lee, Shui-Hun Chen, Jiaw-Ren Shih