Patents by Inventor Junichi Koike

Junichi Koike has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120219724
    Abstract: In a method for forming a metal oxide film, by which excellent adhesion between the film and Cu can be provided, a gas containing an organometallic compound is supplied to a base, and the metal oxide film is formed on the base. After forming the metal oxide film on the base by supplying the organometallic compound to the base, the metal oxide film is exposed to the oxygen-containing gas or oxygen-containing plasma in the final step of the process of forming the metal oxide film.
    Type: Application
    Filed: September 17, 2010
    Publication date: August 30, 2012
    Applicants: TOHOKU UNIVERSITY, TOKYO ELECTRON LIMITED
    Inventors: Koji Neishi, Junichi Koike, Kenji Matsumoto
  • Publication number: 20120211769
    Abstract: A SiC single crystal wafer on which a good quality epitaxial film by suppressing defects derived from the wafer can be grown has an affected surface layer with a thickness of at most 50 nm and a SiC single crystal portion with an oxygen content of at most 1.0×1017 atoms/cm3. This SiC single crystal wafer is manufactured from a high purity SiC bulk single crystal obtained by the solution growth method using raw materials with an oxygen content of at most 100 ppm and a non-oxidizing atmosphere having an oxygen concentration of at most 100 ppm.
    Type: Application
    Filed: February 27, 2012
    Publication date: August 23, 2012
    Applicant: SUMITOMO METAL INDUSTRIES, LTD.
    Inventors: Kazuhiko Kusunoki, Kazuhito Kamei, Nobuyoshi Yashiro, Junichi Koike
  • Patent number: 8247321
    Abstract: When a barrier film is formed on an exposed surface of an interlayer insulation film on a substrate, the interlayer insulation film having a recess formed therein, and a metal wiring to be electrically connected to a metal wiring in a lower layer is formed in the recess, a barrier film having an excellent step coverage can be formed and increase of a wiring resistance can be restrained. An oxide film on a surface of the lower copper wiring exposed to a bottom surface of the interlayer insulation film is reduced or edged so as to remove oxygen on the surface of the copper wiring. Then, by supplying an organic metal compound containing manganese and containing no oxygen, generation of manganese oxide as a self-forming barrier film is selectively allowed on an area containing oxygen, such as a sidewall of the recess and a surface of the interlayer insulation film, while generation of the manganese oxide is not allowed on the surface of the copper wiring. Thereafter, copper is embedded in the recess.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: August 21, 2012
    Assignees: Tokyo Electron Limited, National University Corporation Tohoku University
    Inventors: Kenji Matsumoto, Hitoshi Itoh, Hiroshi Sato, Junichi Koike, Koji Neishi
  • Patent number: 8242015
    Abstract: On a surface of an object to be treated, a Mn-containing thin film or CuMn-containing alloy thin film is formed by heat treatment (CVD or ALD) by using a Mn-containing source gas (or Mn-containing source gas and a Cu-containing gas) and an oxygen-containing gas (for instance, water vapor) as a processing gas. The Mn-containing thin film or the CuMn-containing alloy thin film can be formed with high step coverage in a fine recess formed on the surface of the object to be treated.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: August 14, 2012
    Assignees: Tokyo Electron Limited, Tohoku University
    Inventors: Kenji Matsumoto, Hitoshi Itoh, Koji Neishi, Junichi Koike
  • Publication number: 20120135612
    Abstract: A film forming method is disclosed in which a thin film comprising manganese is formed on an object to be processed which has, on a surface thereof, an insulating layer constituted of a low-k film and having a recess. The method comprises a hydrophilization step in which the surface of the insulating layer is hydrophilized to make the surface hydrophilic and a thin-film formation step in which a thin film containing manganese is formed on the surface of the hydrophilized insulating layer by performing a film forming process using a manganese-containing material gas on the surface of the hydrophilized insulating layer. Thus, a thin film comprising manganese, e.g., an MnOx film, is effectively formed on the surface of the insulating layer constituted of a low-k film, which has a low dielectric constant.
    Type: Application
    Filed: June 16, 2010
    Publication date: May 31, 2012
    Applicants: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY, TOKYO ELECTRON LIMITED
    Inventors: Kenji Matsumoto, Hitoshi Itoh, Hidenori Miyoshi, Shigetoshi Hosaka, Hiroshi Sato, Koji Neishi, Junichi Koike
  • Patent number: 8188599
    Abstract: A semiconductor device enables a barrier layer to fully acquire a barriering property against the diffusion of Cu from a wiring main body and the diffusion of Si from an insulating film, enhances the adhesiveness of the barrier layer and the insulating film and excels in reliability of operation over a long period of time.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: May 29, 2012
    Assignee: Advanced Interconnect Materials, LLC
    Inventor: Junichi Koike
  • Patent number: 8169079
    Abstract: A copper interconnection structure includes an insulating layer, an interconnection body including copper in an opening provided on the insulating layer and a barrier layer including a metal element and copper, formed between the insulating layer and the interconnection body. An atomic concentration of the metal element in the barrier layer is accumulated toward an outer surface of the barrier layer facing the insulating layer, and an atomic concentration of copper in the barrier layer is accumulated toward an inner surface of the barrier layer facing the interconnection body. The inner surface of the barrier layer comprises copper surface orientation of {111} and {200}, and an intensity of X-ray diffraction peak from the inner surface of the barrier layer is stronger for the {111} peak than for the {200} peak.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: May 1, 2012
    Assignee: Advanced Interconnect Materials, LLC
    Inventors: Junichi Koike, Akihiro Shibatomi
  • Patent number: 8164701
    Abstract: In a liquid crystal display (LCD) device having a thin film transistor (TFT), the TFT includes a source electrode, a drain electrode and a semiconductor layer. At least one of the source electrode and drain electrode includes a first layer including copper and a second layer forming an oxide layer and covering the first layer. The semiconductor layer has a substantially linear current-voltage relationship with said source electrode or drain electrode including said first and second layers, when a voltage is applied between the semiconductor layer and said source electrode or drain electrode.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: April 24, 2012
    Assignee: Advanced Interconnect Materials, LLC.
    Inventors: Junichi Koike, Hideaki Kawakami
  • Patent number: 8163649
    Abstract: A copper interconnection structure includes an insulating layer, an interconnection and a barrier layer. The insulating layer includes silicon (element symbol: Si), carbon (element symbol: C), hydrogen (element symbol: H) and oxygen (element symbol: O). The interconnection is located on the insulating layer, and the interconnection includes copper (element symbol: Cu). The barrier layer is located between the insulating layer and the interconnection. The barrier layer includes an additional element, carbon (element symbol: C) and hydrogen (element symbol: H). The barrier layer has atomic concentrations of carbon (element symbol: C) and hydrogen (element symbol: H) maximized in a region of a thickness of the barrier layer where the atomic concentration of the additional element is maximized.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: April 24, 2012
    Assignee: Advanced Interconnect Materials, LLC
    Inventors: Junichi Koike, Akihiro Shibatomi
  • Patent number: 8133813
    Abstract: A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: March 13, 2012
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Junichi Koike, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru
  • Patent number: 8112885
    Abstract: A method for forming a copper interconnection structure includes the steps of forming an opening in an insulating layer, forming a copper alloy layer including a metal element on an inner surface of the opening, and conducting a heat treatment on the copper alloy layer so as to form a barrier layer. An enthalpy of oxide formation for the metal element is lower than the enthalpy of oxide formation for copper. The heat treatment is conducted at temperatures ranging from 327° C. to 427° C. and for a time period ranging from 1 minute to 80 minutes.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: February 14, 2012
    Assignee: Advanced Interconnect Materials, LLC
    Inventors: Junichi Koike, Akihiro Shibatomi
  • Publication number: 20120025380
    Abstract: There is provided a manganese oxide film forming method capable of forming a manganese oxide film having high adhesivity to Cu. In the manganese oxide film forming method, a manganese oxide film is formed on an oxide by supplying a manganese-containing gas onto the oxide. A film forming temperature for forming the manganese oxide film is set to be equal to or higher than about 100° C. and lower than about 400° C.
    Type: Application
    Filed: October 6, 2011
    Publication date: February 2, 2012
    Applicants: TOHOKU UNIVERSITY, TOKYO ELECTRON LIMITED
    Inventors: Koji Neishi, Junichi Koike, Kenji Matsumoto
  • Publication number: 20120021603
    Abstract: A method for forming a copper interconnection structure includes the steps of forming an opening in an insulating layer, forming a copper alloy layer including a metal element on an inner surface of the opening, and conducting a heat treatment on the copper alloy layer so as to form a barrier layer. An enthalpy of oxide formation for the metal element is lower than the enthalpy of oxide formation for copper. The heat treatment is conducted at temperatures ranging from 327° C. to 427° C. and for a time period ranging from 1 minute to 80 minutes.
    Type: Application
    Filed: October 3, 2011
    Publication date: January 26, 2012
    Applicant: Advanced Interconnect Materials, LLC
    Inventors: Junichi KOIKE, Akihiro Shibatomi
  • Publication number: 20120003390
    Abstract: A copper interconnection structure includes an insulating layer, an interconnection body including copper in an opening provided on the insulating layer, and a diffusion barrier layer formed between the insulating layer and the interconnection body. The diffusion barrier layer includes an oxide layer including manganese having a compositional ratio of oxygen to manganese (y/x) less than 2.
    Type: Application
    Filed: September 12, 2011
    Publication date: January 5, 2012
    Applicant: Advanced Interconnect Materials, LLC
    Inventors: Junichi Koike, Akihiro Shibatomi
  • Patent number: 8089158
    Abstract: The present invention includes a liquid crystal display device having an oxide film having high adhesiveness to a substrate to thereby prevent oxidation of a wiring material or the like, and includes, an electrode or a terminal electrode having high conductivity, and a manufacturing method therefor. Consequently, in the present invention, a liquid crystal display device has an electrode terminal of a TFT substrate, wherein the electrode is formed on an insulator and is comprised of a conductive layer mainly consisting of copper and an oxide covering an outer part, further the oxide is a layered structure of transparent electrodes, the layered portion having ohmic contact, and the oxide mainly consists of manganese oxide.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: January 3, 2012
    Assignee: Advanced Interconnect Materials, LLC
    Inventors: Junichi Koike, Hideaki Kawakami
  • Patent number: 8084860
    Abstract: The present invention includes a liquid crystal display device having an oxide film having high adhesiveness to a substrate to thereby prevent oxidation of a wiring material or the like, and includes, an electrode or a terminal electrode having high conductivity, and a manufacturing method therefor. Consequently, in the present invention, a liquid crystal display device has an electrode terminal of a TFT substrate, wherein the electrode is formed on an insulator and is comprised of a conductive layer mainly consisting of copper and an oxide covering an outer part, further the oxide is a layered structure of transparent electrodes, the layered portion having ohmic contact, and the oxide mainly consists of manganese oxide.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: December 27, 2011
    Assignee: Advanced Interconnect Materials, LLC
    Inventors: Junichi Koike, Hideaki Kawakami
  • Publication number: 20110233560
    Abstract: An electrode for silicon carbide includes a silicide region which is provided in contact with a surface of a silicon carbide (SiC) layer and a carbide region which is provided on the silicide region. The silicide region contains a silicide of a first metal in more amount than a carbide of a second metal whose free energy of carbide formation is less than that of silicon (Si). The carbide region contains the carbide of the second metal in more amount than the silicide of the first metal.
    Type: Application
    Filed: March 16, 2011
    Publication date: September 29, 2011
    Applicant: Advanced Interconnect Materials, LLC
    Inventors: Junichi Koike, Akihiro Shibatomi, Kunhwa Jung, Yuji Sutou
  • Patent number: 8008184
    Abstract: A seed layer is formed on a surface of an insulating film and along a recess of the insulating film, and after a copper wiring is buried in the recess, a barrier film is formed, and an excessive metal is removed from the wiring. On a surface of a copper lower layer conductive path exposed at the bottom of the recess, a natural oxide of the copper is reduced or removed. On a substrate from which the natural oxide is reduced or removed, the seed layer, composed of a self-forming barrier metal having oxidative tendency higher than that of copper or an alloy of such metal and copper, is formed. The substrate is heated after burying copper in the recess. Thus, a barrier layer is formed by oxidizing the self-forming barrier metal. An excessive portion of the self-forming barrier metal is deposited on a surface of the buried copper.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: August 30, 2011
    Assignees: Tokyo Electron Limited, Tohoku University
    Inventors: Kenji Matsumoto, Shigetoshi Hosaka, Junichi Koike, Koji Neishi
  • Publication number: 20110189849
    Abstract: A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.
    Type: Application
    Filed: April 14, 2011
    Publication date: August 4, 2011
    Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER
    Inventors: Junichi KOIKE, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru
  • Patent number: 7943517
    Abstract: A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: May 17, 2011
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Junichi Koike, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru