Patents by Inventor Kiyoshi Takeuchi

Kiyoshi Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140084386
    Abstract: A first contact, a second impurity region, and a second low-concentration impurity region form a Schottky barrier diode. The second impurity region has the same impurity concentration as those of first impurity regions, and thus can be formed in the same process as forming the first impurity regions. In addition, the second low-concentration impurity region has the same impurity concentration as those of first low-concentration impurity regions, and thus can be formed in the same process as forming the first low-concentration impurity regions.
    Type: Application
    Filed: September 26, 2013
    Publication date: March 27, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Hiroshi Takeda, Kiyoshi Takeuchi, Takashi Onizawa, Masayasu Tanaka
  • Patent number: 8646376
    Abstract: A plurality of ring-shaped sealing members are spaced from each other on the outer periphery of each of first and second end caps that seal openings of first and second cylinder holes. Ring-shaped flow paths are formed between adjacent ring-shaped sealing members. Parts of air flow paths that supply and discharge compressed air to and from pressure chambers of the cylinder holes are formed by the ring-shaped flow paths.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: February 11, 2014
    Assignee: SMC Corporation
    Inventors: Kiyoshi Takeuchi, Mitsunori Magaribuchi, Kazuhiro Shinohara
  • Publication number: 20140020762
    Abstract: An organic semiconductor polymer having a structural unit represented by the following Formula (I), a composition for organic semiconductor material, a photovoltaic cell and a polymer. wherein X represents Si, S or O; R1 represents a hydrogen atom, an alkyl group, a cycloalkyl group, an aryl group, an aromatic heterocyclic group or an oxygen atom; p represents 0, 1 or 2; herein, the bond between X and R1 is such that when X is Si, the bond is a single bond, and when X is S, the bond is a double bond. Furthermore, when X is O, p represents 0.
    Type: Application
    Filed: September 24, 2013
    Publication date: January 23, 2014
    Applicant: FUJIFILM Corporation
    Inventors: Yoshihiro NAKAI, Hiroki SUGIURA, Naoyuki HANAKI, Kiyoshi TAKEUCHI
  • Publication number: 20140026043
    Abstract: A computer-readable recording medium stores an input support program that causes a computer to execute a process that includes detecting a nearby character string of one character or more included in an area within a predetermined range of a selected input area on an image displayed on a screen; searching a database correlating and storing item names indicating input items and text examples corresponding to the input items, for a text example that is correlated with an item name indicating an input item corresponding to the detected nearby character string and that corresponds to the character string, upon receiving input of a character string of one character or more to the input area; and outputting as a conversion candidate of the character string, the text example retrieved at the searching.
    Type: Application
    Filed: April 16, 2013
    Publication date: January 23, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Kiyoshi TAKEUCHI
  • Publication number: 20140021456
    Abstract: An organic semiconductor polymer comprising a structural unit represented by the following Formula (I), a composition for organic semiconductor material, a photovoltaic cell and a polymer. wherein Z1 and Z2 each independently represent S, O, Se or Te; R represents —SOpX, —CN, —NO2, —P(?O)(OR1)(OR2) or —C(R1?)?C(CN)2; X represents a hydrogen atom, an alkyl group, a cycloalkyl group, an aryl group, an aromatic heterocyclic group or —NR3(R4); R1, R2, R1, R3 and R4 each independently represent a hydrogen atom, an alkyl group, a cycloalkyl group, an aryl group or an aromatic heterocyclic group; R3 and R4 may bond with each other to form a ring; and p represents 1 or 2.
    Type: Application
    Filed: September 24, 2013
    Publication date: January 23, 2014
    Applicant: FUJIFILM Corporation
    Inventors: Yoshihiro NAKAI, Hiroki SUGIURA, Kiyoshi TAKEUCHI
  • Patent number: 8592686
    Abstract: A method for manufacturing a printed circuit board assembled panel by a simple process with an excellent material yield and a high conforming product rate. Unit printed circuit boards previously manufactured are arranged in a frame in a prescribed relationship. Then, the printed circuit boards are fixed to one another, and the printed circuit board and the frame body are fixed to one another.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: November 26, 2013
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Atsushi Kobayashi, Kazuo Umeda, Wataru Gotou, Takahiro Sahara, Susumu Nakazawa, Kiyoshi Takeuchi, Takayuki Terauchi
  • Patent number: 8581333
    Abstract: A first local wiring includes a convex portion protruding from a base and a protrusion protruding from a side surface of the convex portion. The convex portion of the first local wiring is connected to a lower conductive region of a first transistor while the protrusion is connected to a gate electrode of a second transistor. Moreover, the lower surface of the protrusion of the first local wiring is arranged at a height equal to or lower than the upper surface of the gate electrode of the second transistor.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: November 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Kiyoshi Takeuchi
  • Publication number: 20130220686
    Abstract: A multilayered printed wiring board includes a plurality of insulating layers; a plurality of wiring layers which are located between the corresponding adjacent insulating layers; and a plurality of interlayer connection conductors for electrically connecting the wiring layers through the insulating layers; wherein a cavity is formed through one or more of the insulating layers so as to insert a first electric/electronic component and an area for embedding a second electric/electronic component is defined for the insulating layers.
    Type: Application
    Filed: February 14, 2013
    Publication date: August 29, 2013
    Inventors: Takahiro Sahara, Atsushi Kobayashi, Kiyoshi Takeuchi, Masahiko Igaue
  • Patent number: 8476535
    Abstract: A multilayered printed wiring board includes a flexible wiring board with wiring layers on both main surfaces thereof; a rigid wiring board with wiring layers on both main surfaces thereof and formed opposite to the flexible wiring board under the condition that an area of the main surface of the rigid wiring board is smaller than an area of the main surface of the flexible wiring board; and an electric/electronic component embedded in the rigid wiring board.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: July 2, 2013
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Takahiro Sahara, Atsushi Kobayashi, Masahiko Igaue, Kiyoshi Takeuchi
  • Publication number: 20130076618
    Abstract: An exemplary information processing apparatus selectively switches between: first control where control is performed such that, in a virtual space, a position of producing no parallax on a screen of a stereoscopic display is a first position near a predetermined object; and second control where control is performed such that the position of producing no parallax is closer to a viewpoint position of virtual cameras than the first position is.
    Type: Application
    Filed: June 27, 2012
    Publication date: March 28, 2013
    Applicant: Nintendo Co., Ltd.
    Inventors: Shigeru MIYAMOTO, Koichi HAYASHIDA, Kiyoshi TAKEUCHI
  • Patent number: 8400776
    Abstract: A multilayered printed wiring board includes a plurality of insulating layers; a plurality of wiring layers which are located between the corresponding adjacent insulating layers; and a plurality of interlayer connection conductors for electrically connecting the wiring layers through the insulating layers; wherein a cavity is formed through one or more of the insulating layers so as to insert a first electric/electronic component and an area for embedding a second electric/electronic component is defined for the insulating layers.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: March 19, 2013
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Takahiro Sahara, Atsushi Kobayashi, Kiyoshi Takeuchi, Masahiko Igaue
  • Publication number: 20130031095
    Abstract: A computer-readable recording medium has an entry support program embodied therein for causing a computer to perform detecting text being entered, extracting text examples corresponding to the detected text from a storage unit, the storage unit storing text examples and frequencies of use of the text examples such that the frequencies of use are associated with the respective text examples, classifying the extracted text examples into text-example groups each containing one or more text examples based on comparison of letters included in the extracted text examples, determining display order of the text-example groups, based on the frequencies of use that are associated in the storage unit with text examples belonging to the text-example groups, and displaying the extracted text examples in the determined display order.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 31, 2013
    Applicant: FUJITSU LIMITED
    Inventor: Kiyoshi Takeuchi
  • Publication number: 20120313172
    Abstract: This invention is to provide a semiconductor device having a reduced variation in the transistor characteristics. The semiconductor device has a SOI substrate, a first element isolation insulating layer, first and second conductivity type transistors, and first and second back gate contacts. The SOI substrate has a semiconductor substrate having first and second conductivity type layers, an insulating layer, and a semiconductor layer. The first element isolation insulating layer is buried in the SOI substrate, has a lower end reaching the first conductivity type layer, and isolates a first element region from a second element region. The first and second conductivity type transistors are located in the first and second element regions, respectively, and have respective channel regions formed in the semiconductor layer. The first and second back gate contacts are coupled to the second conductivity type layers in the first and second element regions, respectively.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 13, 2012
    Inventors: Masaharu MATSUDAIRA, Toshiharu Nagumo, Hiroshi Takeda, Kiyoshi Takeuchi
  • Publication number: 20120311484
    Abstract: In an exemplary image generation system, a virtual camera is set in accordance with a position and an orientation of an object in a virtual space. While a predetermined operation is being performed, an orientation of a display device is detected by using an angular velocity sensor provided in the display device, and an orientation of the virtual camera is changed based on the detected orientation. When the predetermined operation is not performed, the virtual camera is positioned based on an original orientation which is determined in accordance with the position and the orientation of the object.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 6, 2012
    Applicant: NINTENDO CO., LTD.
    Inventors: Yusuke Amano, Kiyoshi Takeuchi, Koichi Hayashida
  • Publication number: 20120306857
    Abstract: One embodiment of a present invention causes a computer to execute controlling a position of an object in the virtual space, determining an area where the object is positioned from among a plurality of areas set in the virtual space, setting a stereoscopic parameter which is used for rendering a stereoscopic image according to the determined area, generating a stereoscopic image including the object based on the set stereoscopic parameter, and displaying the generated stereoscopic image on the display device.
    Type: Application
    Filed: October 11, 2011
    Publication date: December 6, 2012
    Applicant: NINTENDO CO., LTD.
    Inventors: Koichi HAYASHIDA, Hideyuki Sugawara, Kenta Motokura, Kiyoshi Takeuchi
  • Publication number: 20120306868
    Abstract: When a game process is performed by an exemplary game apparatus having an LCD for displaying a stereoscopically visible image, angular velocities of rotations about axes of the game apparatus are detected by using an angular velocity sensor provided in the game apparatus. A stereoscopic effect of a stereoscopically displayed image is adjusted in accordance with a magnitude of a rotation angle of the game apparatus in a roll direction calculated based on the angular velocities of the rotations about axes of the game apparatus.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 6, 2012
    Applicant: NINTENDO CO., LTD.
    Inventors: Kiyoshi TAKEUCHI, Koichi Hayashida
  • Patent number: 8247294
    Abstract: A constant distance can be maintained between source/drain regions without providing a gate side wall by forming a gate electrode including an eaves structure, and a uniform dopant concentration is kept within a semiconductor by ion implantation. As a result, a FinFET excellent in element properties and operation properties can be obtained. A field effect transistor, wherein a gate structure body is a protrusion that protrudes toward source and drain regions sides in a channel length direction and has a channel length direction width larger than that of the part adjacent to the insulating film in a gate electrode, and the protrusion includes an eaves structure formed by the protrusion that extends in a gate electrode extending direction on the top surface of the semiconductor layer.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: August 21, 2012
    Assignee: NEC Corporation
    Inventors: Kiyoshi Takeuchi, Katsuhiko Tanaka
  • Publication number: 20120202330
    Abstract: The present invention provides a semiconductor device including SRAM cell units each including a data holding section made up of a pair of driving transistors and a pair of load transistors, a data write section made up of a pair of access transistors, and a data read section made up of an access transistor and a driving transistor, wherein each of the transistors includes a semiconductor layer projecting upward from a base plane, a gate electrode extending from a top to opposite side surfaces of the semiconductor layer so as to stride the semiconductor layer, a gate insulating film between the gate electrode and the semiconductor layer, and source/drain areas, a longitudinal direction of each of the semiconductor layers is provided along a first direction, and for all the corresponding transistors between the SRAM cell units adjacent to each other in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer along the first dire
    Type: Application
    Filed: February 7, 2012
    Publication date: August 9, 2012
    Applicant: NEC CORPORATION
    Inventors: Koichi TAKEDA, Kiyoshi TAKEUCHI
  • Patent number: D660333
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: May 22, 2012
    Assignee: SMC Corporation
    Inventors: Kiyoshi Takeuchi, Takaaki Kobayashi
  • Patent number: D660334
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: May 22, 2012
    Assignee: SMC Corporation
    Inventors: Kiyoshi Takeuchi, Toshikazu Tabuchi