Abstract: An evaluation method of a semiconductor device according to an aspect of the present invention includes MISFETs including a gate insulating film, the evaluation method including measuring an RTN of a plurality of MISFETs, and extracting at least two parameters selected from a position of a trap in the gate insulating film, an energy of the trap, an RTN time constant, and an RTN amplitude based on a measurement result of the RTN, and obtaining a correlation between these at least two parameters.

Abstract: The present invention provides a semiconductor device including SRAM cell units each including a data holding section made up of a pair of driving transistors and a pair of load transistors, a data write section made up of a pair of access transistors, and a data read section made up of an access transistor and a driving transistor, wherein each of the transistors includes a semiconductor layer projecting upward from a base plane, a gate electrode extending from a top to opposite side surfaces of the semiconductor layer so as to stride the semiconductor layer, a gate insulating film between the gate electrode and the semiconductor layer, and source/drain areas, a longitudinal direction of each of the semiconductor layers is provided along a first direction, and for all the corresponding transistors between the SRAM cell units adjacent to each other in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer along the first dire

Abstract: A variation simulation system providing for facilitated circuit design with suppressed deterioration in performance otherwise caused by variations. A variation analysis unit 100 extracts statistical features of variations from a large number of samples beforehand. A model analysis unit 200 checks response of a circuit simulation output to parameter variations. A fitting execution unit 300 collates the information, obtained in this manner, to each other to determine the manner of variations of the parameters which will reproduce statistical features of the device samples.

Abstract: A sensor is provided. The sensor includes semiconductor layer; a photodiode, an impurity-doped polycrystalline silicon layer; and a gate electrode. The photodiode is formed in the semiconductor layer. The impurity-doped polycrystalline silicon layer is formed above the semiconductor layer. The gate electrode applies a gate voltage to the polycrystalline silicon layer. A wiring layer is provided on a first surface of the semiconductor layer and light is incident on a second surface thereof.

Abstract: A method of testing the operational margin of an information storage device having marked random variations, and an information storage device having the function of self-diagnosing the operational margin, are provided. The test method includes testing an information storage device including a plurality of memory bits as the test condition is set so as to be outside a range of conditions that may be presupposed in real use of the information storage device and of counting the number of memory bits that fail in operation. The test method also includes verifying the size of the operational margin of the information storage device based on the count value. The test condition is made severe and the reference value is set to a fairly large value to enable the operational margin against the noise to be tested highly accurately.

Abstract: A multilayered printed wiring board includes a flexible wiring board with wiring layers on both main surfaces thereof; a rigid wiring board with wiring layers on both main surfaces thereof and formed opposite to the flexible wiring board under the condition that an area of the main surface of the rigid wiring board is smaller than an area of the main surface of the flexible wiring board; and an electric/electronic component embedded in the rigid wiring board.

Abstract: A constant distance can be maintained between source/drain regions without providing a gate side wall by forming a gate electrode including an eaves structure, and a uniform dopant concentration is kept within a semiconductor by ion implantation. As a result, a FinFET excellent in element properties and operation properties can be obtained. A field effect transistor, wherein a gate structure body is a protrusion that protrudes toward source and drain regions sides in a channel length direction and has a channel length direction width larger than that of the part adjacent to the insulating film in a gate electrode, and the protrusion includes an eaves structure formed by the protrusion that extends in a gate electrode extending direction on the top surface of the semiconductor layer.

Abstract: An SRAM cell using a vertical MISFET is provided, wherein underside source/drain areas of a first access transistor, a first driving transistor and a first load transistor are connected together, and further connected to gates of a second driving transistor and a second load transistor. Underside source/drain areas of a second access transistor, the second driving transistor and the second load transistor are connected together, and further connected to gates of the first driving transistor and the first load transistor. A first arrangement of the first access transistor, the first driving transistor and the first load transistor, and a second arrangement of the second access transistor, the second driving transistor and the second load transistor are symmetric to each other.

Abstract: A first local wiring includes a convex portion protruding from a base and a protrusion protruding from a side surface of the convex portion. The convex portion of the first local wiring is connected to a lower conductive region of a first transistor while the protrusion is connected to a gate electrode of a second transistor. Moreover, the lower surface of the protrusion of the first local wiring is arranged at a height equal to or lower than the upper surface of the gate electrode of the second transistor.

Abstract: A constant distance can be maintained between source/drain regions without providing a gate side wall by forming a gate electrode comprising an eaves structure, and a uniform dopant concentration is kept within a semiconductor by ion implantation. As a result, a FinFET excellent in element properties and operation properties can be obtained. A field effect transistor, wherein a gate structure body is a protrusion that protrudes toward source and drain regions sides in a channel length direction and has a channel length direction width larger than that of the part adjacent to the insulating film in a gate electrode, and the protrusion comprises an eaves structure formed by the protrusion that extends in a gate electrode extending direction on the top surface of the semiconductor layer.

Abstract: A semiconductor device is provided with an SRAM cell unit. The SRAM cell unit is provided with a data storing section composed of a pair of drive transistors and a pair of load transistors; a data write section composed of a pair of access transistors; and a data read section composed of an access transistor and a drive transistor. Each of the transistors is provided with a semiconductor layer protruding from a base plane; a gate electrode extending on the both facing side planes over the semiconductor layer from above; a gate insulating film between a gate electrode and a semiconductor layer; and a source/drain region. Each semiconductor layer is arranged to have its longitudinal direction along a first direction. In the adjacent SRAM cell units in the first direction, all the corresponding transistors have the semiconductor layer of one transistor on a center line which is along the first direction of the semiconductor layer of the other transistor.

Abstract: A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.

Abstract: A rigid-flexible board and a method for manufacturing the same can be provided, whereby the material yield ratio can be enhanced and the productive yield can be also enhanced. A rigid board with a step for connection and a flexible board with a connector at the edge thereof are formed independently. Then, the connecting area is spot facing processed so that the depth of the thus obtained depressed portion is equal to or lower than the thickness of the flexible board. The connector of the flexible board is electrically connected to the vertical wiring area of the depressed portion.

Abstract: Disclosed is a variation simulation system including a variation analysis unit that acquires the results of statistical analysis of variations of characteristics of a plural number of target devices, a model analysis unit that acquires the results of analysis showing how the characteristics respond to variations of a parameter with respect to a model for simulation that simulates each target device, a fitting execution unit that collates the results obtained by the variation analysis unit to those obtained by the model analysis unit and determines the manner of variations of the parameter in order to reproduce the variations of each target device in accordance with the model, and a result output unit that outputs the information on the manner of variations of the parameter determined by the fitting execution unit. A transformation matrix is determined by multiplying a pseudo inverse matrix of a response matrix, a matrix made up of principal component vectors and an arbitrary unitary matrix.

Abstract: The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a p

Abstract: A semiconductor device comprising a first semiconductor region and a second semiconductor region, (a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s), (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.

Abstract: A silver halide color photographic light-sensitive material having, on a support, at least each one light-sensitive silver halide emulsion layers containing yellow-, magenta-, or cyan-dye-forming-coupler, and at least one light-insensitive hydrophilic colloid layer, wherein at least one of the dye-forming couplers is a dye-forming coupler that forms an azomethine dye having a solubility of 1×10?8 mol/L to 5×10?3 mol/L in ethyl acetate; and an image forming method using the light-sensitive material.

Abstract: A system for determining a worst condition, wherein, in a model for which one or more parameters included in a model function that simulates a circuit performance index are random variable(s) to simulate the circuit performance index and fluctuations thereof, the parameter(s) for which the circuit performance index assumes a maximum or minimum value that is to be assumed from the viewpoint of designing is determined as the worst condition; the system comprises a worst condition search unit that searches for a point, having a maximum or minimum value of the circuit performance index, on an equi-probability surface corresponding to a preset good product ration within a space defined by the parameter(s); the point thus searched being determined as the worst condition.

Abstract: A plurality of ring-shaped sealing members are spaced from each other on the outer periphery of each of first and second end caps that seal openings of first and second cylinder holes. Ring-shaped flow paths are formed between adjacent ring-shaped sealing members. Parts of air flow paths that supply and discharge compressed air to and from pressure chambers of the cylinder holes are formed by the ring-shaped flow paths.

Abstract: A semiconductor device has: an insulating substrate; a first semiconductor layer of a first conductivity type formed on the insulating substrate; a first vertical field effect transistor of the first conductivity type, one of whose source and drain being formed on the first semiconductor layer; a second semiconductor layer of a second conductivity type formed on the insulating substrate; and a second vertical field effect transistor of the second conductivity type, one of whose source and drain being formed on the second semiconductor layer. The first semiconductor layer and the second semiconductor layer are directly in contact with each other.