Abstract: A paste and a damp-heat (DH) attenuation resistant photovoltaic cell. The paste comprises a paste body, into which an inert metal element and an oxide thereof are added, so that a barrier layer having a certain thickness can be formed on the surface of an electrode after sintering, and the barrier layer can resist oxidation and corrosion so as to enhance the oxidation resistance and the acid corrosion resistance of the metallized electrode. The electrode of the photovoltaic cell is made of the paste, and the DH attenuation resistant photovoltaic cell made of the paste can reduce DH attenuation and power loss, and has the enhanced environmental protection property and reliability.

Abstract: In a method of manufacturing a semiconductor device, sacrificial patterns are formed over a hard mask layer disposed over a substrate, sidewall patterns are formed on sidewalls of the sacrificial patterns, the sacrificial patterns are removed, thereby leaving the sidewall patterns as first hard mask patterns, the hard mask layer is patterned by using the first hard mask patters as an etching mask, thereby forming second hard mask patterns, and the substrate is patterned by using the second hard mask patterns as an etching mask, thereby forming fin structures. Each of the first sacrificial patterns has a tapered shape having a top smaller than a bottom.

Abstract: Disclosed is a barrier-type photovoltaic solder strip capable of reducing damp-heat (DH) attenuation, the photovoltaic solder strip comprising a photovoltaic solder strip body. A moisture barrier layer is arranged on a surface of the photovoltaic solder strip body that is not in contact with an electrode of a solar cell, and the moisture barrier layer can prevent external water and gas from entering the photovoltaic solder strip body, thus, on the basis of low cost, corrosion of the photovoltaic solder strip body by acidic substances, oxidizing agents and water in a module is reduced, thereby reducing attenuation of a photovoltaic module in a DH environment.

Abstract: Digital content view control is described as leveraging a hierarchical structure of objects defined within the digital content to control how those objects are rendered in a user interface. In one example, a user input is received to display a view of objects within digital content displayed in a user interface. In response, a data query module is configured to fetch data describing a hierarchical structure of the digital content. From this, a z-order determination module determines a z-order of objects included with the digital content. An object view generation module is also configured to generate object views depicting the objects included in the digital content. The object views, once rendered, support an ability to view positioning of objects within the hierarchy.

Abstract: A graft polymer is provided, which includes a polymer backbone with a plurality of hydroxy groups, protection group modified histidine grafted onto the side of the polymer backbone, and hydrophilic polymer having terminal reactive group grafted onto the side of the polymer backbone. The graft polymer coating can be applied to metal material to form a composite material, which can be implanted into an organism to reduce adhesion problems.

Abstract: An artificial neural network-based method for detecting a surface type of an object includes: receiving a plurality of object images, wherein a plurality of spectra of the plurality of object images are different from one another and each of the object images has one of the spectra; transforming each object image into a matrix, wherein the matrix has a channel value that represents the spectrum of the corresponding object image; and executing a deep learning program by using the matrices to build a predictive model for identifying a target surface type of the object. Accordingly, the speed of identifying the target surface type of the object is increased, further improving the product yield of the object.

Abstract: Provided are a solar cell, a manufacturing method thereof, and a photovoltaic module. The solar cell includes: a semiconductor substrate, in which a rear surface of the semiconductor substrate having a first texture structure, the first texture structure includes two or more first substructures at least partially stacked on one another, and a one-dimensional size of the top surface of the outermost first substructure is less than or equal to 45 ?m; a first passivation layer located on a front surface of the semiconductor substrate; a tunnel oxide layer located on the first texture structure; a doped conductive layer located on a surface of the tunnel oxide layer, the doped conductive layer includes a P-type doped conductive layer and an N-type doped conductive layer; and a second passivation layer located on a surface of the doped conductive layer.

Abstract: An artificial neural network-based method for selecting a surface type of an object is suitable for selecting a plurality of objects. The artificial neural network-based method for selecting a surface type of an object includes performing surface type identification on a plurality of object images by using a plurality of predictive models to obtain a prediction defect rate of each of the predictive models, wherein the object images correspond to surface types of a part of the objects, and cascading the predictive models according to the respective prediction defect rates of the predictive models into an artificial neural network so as to select the remaining objects.

Abstract: An artificial neural network-based method for detecting a surface type of an object includes: receiving a plurality of object images, wherein a plurality of spectra of the plurality of object images are different from one another and each of the object images has one of the spectra; transforming each object image into a matrix, wherein the matrix has a channel value that represents the spectrum of the corresponding object image; and executing a deep learning program by using the matrices to build a predictive model for identifying a target surface type of the object. Accordingly, the speed of identifying the target surface type of the object is increased, further improving the product yield of the object.

Abstract: The present invention provides a system and method for analysis of integrated circuit testing anomalies based on deep learning. Through repeated training by deep learning with historical test data accumulated during testing, automatic optimization of parameter settings depending on learning and training conditions is made possible. Moreover, based on real-time test data, testing anomalies can be predicted and early warnings against them can be provided to allow advanced intervention for preventing their occurrence. Additionally, for testing anomalies that have occurred, solutions can be automatically identified and provided, which shorten the times taken by different technicians to address the anomalies, resulting in more effective utilization of the equipment and lower testing cost.

Abstract: The present disclosure discloses a human body simulation model, a fitting device, a fitting server, and a control method. The human body simulation model includes: a human body model; a photodeformable shaping garment; a plurality of excitation light sources; a plurality of elastic elements; and a first controller configured to control at least a part of the plurality of excitation light sources to emit light waves to the photodeformable shaping garment according to body shape parameters of a user received, so that the photodeformable shaping garment is deformed to simulate a body shape of the user.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a material layer over a semiconductor substrate; forming a plurality of spacer masks over the material layer; patterning the material layer into a plurality of masks below the spacer masks, wherein patterning the material layer comprises an atomic layer etching (ALE) process; and etching the semiconductor substrate through the masks.

Abstract: Provided is a photovoltaic solar cell, a solar cell module and a manufacturing process. The photovoltaic solar cell includes a silicon substrate, and a passivation layer located on at least one surface of the silicon substrate. An electrode, an electrode pad and an extension line are printed on at least one surface of the silicon substrate. The electrode includes a busbar and a finger crossed with each other, and the finger is in contact with the silicon substrate. Two ends of the extension line are respectively connected to the busbar and the electrode pad, and the extension line is in contact with the silicon substrate.

Abstract: Provided are a solar cell, a manufacturing method thereof, and a photovoltaic module. The solar cell includes: a semiconductor substrate, in which a rear surface of the semiconductor substrate having a first texture structure, the first texture structure includes two or more first substructures at least partially stacked on one another, and in a direction away from the rear surface and perpendicular to the rear surface, a distance between a top surface of an outermost first substructure and a top surface of an adjacent first substructure being less than or equal to 2 ?m; a first passivation layer located on a front surface of the semiconductor substrate; a tunnel oxide layer located on the first texture structure; a doped conductive layer located on a surface of the tunnel oxide layer; and a second passivation layer located on a surface of the doped conductive layer.

Abstract: Provided are a solar cell, a manufacturing method thereof, and a photovoltaic module. The solar cell includes: a semiconductor substrate, in which a rear surface of the semiconductor substrate having a first texture structure, the first texture structure includes two or more first substructures at least partially stacked on one another, and in a direction away from the rear surface and perpendicular to the rear surface, a distance between a top surface of an outermost first substructure and a top surface of an adjacent first substructure being less than or equal to 2?m; a first passivation layer located on a front surface of the semiconductor substrate; a tunnel oxide layer located on the first texture structure; a doped conductive layer located on a surface of the tunnel oxide layer; and a second passivation layer located on a surface of the doped conductive layer.

Abstract: A semiconductor device includes a substrate, a pair of semiconductor fins, a dummy fin structure, a gate structure, a plurality of source/drain structures, a crystalline hard mask layer, and an amorphous hard mask layer. The pair of semiconductor fins extend upwardly from the substrate. The dummy fin structure extends upwardly above the substrate and is laterally between the pair of semiconductor fins. The gate structure extends across the pair of semiconductor fins and the dummy fin structure. The source/drain structures are above the pair of semiconductor fins and on either side of the gate structure. The crystalline hard mask layer extends upwardly from the dummy fin and has an U-shaped cross section. The amorphous hard mask layer is in the first hard mask layer, wherein the amorphous hard mask layer having an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Abstract: An ester compound which can be used as the additive of the lubricating oil or the base oil of the lubricating oil, and a process for preparing the same and use thereof are provided. The ester has excellent viscosity-temperature properties and low-temperature properties and can be used as the base oil of the lubricating oil. In addition, the ester compound has excellent viscosity-temperature properties and low-temperature properties as the viscosity index improver, can significantly reduce the wear scar diameter of the base oil as the anti-wear agent, can significantly reduce the friction coefficient of the base oil as the friction modifier, and exhibits excellent anti-wear and anti-friction properties.

Abstract: A flyback power converter circuit includes a transformer, a blocking switch, a primary side switch, a primary side controller circuit and a secondary side controller circuit. The transformer is coupled between an input voltage and an internal output voltage in an isolated manner. The blocking switch controls the electric connection between the internal output voltage and an external output voltage. In a standby mode, the internal output voltage is regulated to a standby voltage, and the blocking switch is controlled to be OFF; in an operation mode, the internal output voltage is regulated to an operating voltage, and the blocking switch is controlled to be ON, such that the external output voltage has the operating voltage. The standby voltage is smaller than the operating voltage, so that the power consumption of the flyback power converter circuit is reduced in the standby mode.

Abstract: A DNS (Domain Name Server) proxy is configured as a DNS server for clients on the enterprise network to send two or more DNS queries to collect each available IP addresses on a SDWAN member link. IP address collection can be responsive to receiving a DNS request from a client for assigning a FQDN (Fully Qualified Domain Name). Service quality can be evaluated for the service on each member link of the IP addresses. An IP address is assigned to the client based on the service quality evaluation. A notification is transmitted to the client in a DNS response to the IP address request, with the chosen IP address information for configuration.