Abstract: A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.

Abstract: A structure and formation method of a semiconductor device is provided. The semiconductor device structure includes an epitaxial structure over a semiconductor substrate. The semiconductor device structure also includes a dielectric fin over the semiconductor substrate. The dielectric fin extends upwards to exceed a bottom surface of the epitaxial structure. The dielectric fin has a dielectric structure and a protective shell, and the protective shell extends along sidewalls and a bottom of the dielectric structure. The protective shell has a first average grain size, and the dielectric structure has a second average grain size. The first average grain size is larger than the second average grain size.

Abstract: A method includes providing a substrate having a first semiconductor material; creating a mask that covers an nFET region of the substrate; etching a pFET region of the substrate to form a trench; epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, wherein the first fin includes the first semiconductor material and the second fin includes a top portion over a bottom portion, wherein the top portion includes the second semiconductor material, and the bottom portion includes the first semiconductor material.

Abstract: In a method of manufacturing a semiconductor device, sacrificial patterns are formed over a hard mask layer disposed over a substrate, sidewall patterns are formed on sidewalls of the sacrificial patterns, the sacrificial patterns are removed, thereby leaving the sidewall patterns as first hard mask patterns, the hard mask layer is patterned by using the first hard mask patters as an etching mask, thereby forming second hard mask patterns, and the substrate is patterned by using the second hard mask patterns as an etching mask, thereby forming fin structures. Each of the first sacrificial patterns has a tapered shape having a top smaller than a bottom.

Abstract: A flyback converter includes a power transformer, a primary side switch, a secondary side switch and a controller. A secondary side switching signal has an SR pulse for achieving synchronous rectification, and a ZVS pulse for achieving zero voltage switching. The ZVS pulse is enabled according to a first characteristic of a resonance waveform, whereas, a primary side switching signal is enabled according to a second characteristic of resonance waveform. When an output current increases, the primary side switching signal is disabled during an inhibition interval, such that primary side switching signal does not overlap with the ZVS pulse, thereby preventing the primary and secondary side switches from being both conductive simultaneously. The inhibition interval is correlated with a rising edge of the primary side switching signal in a previous switching period and a resonance period of the resonance waveform.

Abstract: An embodiment of the present disclosure provides an array substrate, a display panel, and a display device, including a substrate, a data line located above the substrate, and a shielding member located on a side, away from the substrate, of the data line, the shielding member includes a conductive screening portion, an orthographic projection of the conductive screening portion on the substrate partially covering an orthographic projection of the data line on the substrate, or the shielding member includes a filling body, an orthographic projection of the filling body on the substrate covering an orthographic projection of the data line on the substrate, and the filling body protruding outward from a surface of the substrate in a direction away from the substrate.

Abstract: A flyback power converter circuit includes: a power transformer, a primary side switch and a conversion control circuit. In a DCM, during a dead time, the conversion control circuit calculates an upper limit frequency corresponding to output current according to a frequency upper limit function, and obtains a frequency upper limit masking period according to a reciprocal of the upper limit frequency, wherein the frequency upper limit masking period is a period starting from when the primary side switch is turned ON. During an upper limit selection period, the conversion control circuit selects a valley among one or more valleys in a ringing signal related to a voltage across the primary side switch as an upper limit locked valley, so that the conversion control circuit once again turns ON the primary side switch at a beginning time point of the upper limit locked valley.

Abstract: A resonance element supported by a bearing structure includes a crystal chip and an excitation electrode. The crystal chip includes a main surface having a support surface portion being in contact with the bearing structure. The excitation electrode is disposed on the main surface, has an electrode area, and includes an electrode indentation boundary partly encompassing the support surface portion. The electrode indentation boundary has a first boundary end and a second boundary end being opposite to the first boundary end. The electrode indentation boundary and a reference line segment defined by the first and the second boundary ends form an electrode indentation region having an indentation area. A ratio of the indentation area to the electrode area ranges from 0.05 to 0.2.

Abstract: A display panel, a mask plate, a method for manufacturing the display panel, and a display device are provided. The display panel includes a display area and a peripheral area surrounding the display area, and the display panel further includes: at least two integrated chips located in the peripheral area of the display area and arranged along a boundary direction of the display area; at least one flow rate regulating structure is respectively located between two adjacent integrated chips and located on a side of the integrated chips remote from the display area, and the flow rate regulating structure is configured to adjust a flow rate of process liquid.

Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, and a light-sensing region close to the front surface. The image sensor device includes an insulating layer covering the back surface and extending into the semiconductor substrate. The protection layer has a first refractive index, and the first refractive index is less than a second refractive index of the semiconductor substrate and greater than a third refractive index of the insulating layer, and the protection layer conformally and continuously covers the back surface and extends into the semiconductor substrate. The image sensor device includes a reflective structure surrounded by insulating layer in the semiconductor substrate.

Abstract: Techniques related to training and implementing a bidirectional pairing architecture for object detection are discussed. Such techniques include generating a first enhanced feature map for each frame of a video sequence by processing the frames in a first direction, generating a second enhanced feature map for frame by processing the frames in a second direction opposite the first, and determining object detection information for each frame using the first and second enhanced feature map for the frame.

Abstract: A resonant half-bridge flyback power converter includes: a power transformer and a resonant capacitor which are coupled in series between a half-bridge power stage and an output power; and a primary controller circuit controlling a high side power switch and a low side power switch of the half-bridge power stage. When the high side switch is OFF, the control signal of the low side power switch includes a resonant switching pulse for achieving resonant switching of the low side switch and a soft switching pulse for achieving ZVS of the high side switch. When the output power is lower than a delay threshold, the primary controller circuit determines a delay period which is between the resonant switching pulse and the soft switching pulse to control both the high side power switch and the low side power switch to be OFF. The delay period is negatively correlated with the output power.

Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

Abstract: A method includes etching a semiconductor substrate to form a trench, filling a dielectric layer into the trench, with a void being formed in the trench and between opposite portions of the dielectric layer, etching the dielectric layer to reveal the void, forming a diffusion barrier layer on the dielectric layer, and forming a high-reflectivity metal layer on the diffusion barrier layer. The high-reflectivity metal layer has a portion extending into the trench. A remaining portion of the void is enclosed by the high-reflectivity metal layer.

Abstract: The present invention relates to a traffic situation detecting method. The method includes steps of acquiring a current location, a speed of movement and a direction of movement for a ground vehicle; using the current location as a starting point and drawing a detecting scope on a digital map toward the direction of movement; varying a size of the detecting scope in adaptive to an interval of the speed to which the speed of movement belongs; accessing a traffic server to retrieve a traffic event and determining whether the traffic event is situated within the detecting scope; and marking the traffic event located within the detecting scope on a digital map.

Abstract: System and techniques are provided for three-dimension (3D) semantic segmentation. A device for 3D semantic segmentation includes: an interface, to obtain a point cloud data set for a time-ordered sequence of 3D frames, the 3D frames including a current 3D frame and one or more historical 3D frames previous to the current 3D frame; and processing circuitry, to: invoke a first artificial neural network (ANN) to estimate a 3D scene flow field for each of the one or more historical 3D frames by taking the current 3D frame as a reference frame; and invoke a second ANN to: produce an aggregated feature map, based on the reference frame and the estimated 3D scene flow field for each of the one or more historical 3D frames; and perform the 3D semantic segmentation based on the aggregated feature map.

Abstract: There is disclosed a method for mitigating phishing risk to a recipient of a phishing electronic document. The method comprises receiving (302) the phishing electronic document (108) intended for the recipient (104) and identifying (304) parameters in the phishing electronic document. The parameters are applied (306) to a customised risk profile of the recipient to generate a risk index. The risk index is then compared (308) to a specified risk threshold. A phishing alert based on the comparison is generated (310) and provided (312) to the recipient along with the electronic document.

Abstract: System and methods may be used for arc fluence optimization without iteration to arc sequence generation. A method may include defining a particle arc range for a radiotherapy treatment of a patient, and generating an arc sequence, including a set of parameters for delivering the radiotherapy treatment, without requiring a dose calculation. The method may include optimizing fluence of the arc sequence for the radiotherapy treatment without iterating back to arc sequence generation, and outputting the fluence optimized arc sequence for use in the radiotherapy treatment.

Abstract: Systems, apparatuses and methods (30) may provide for technology that stores data associated with a plurality of intermediate operations in an autonomous vehicle process (32), generates a visualization output based at least partly on the data (34), and changes a magnification level of the visualization output based on user input (38), the visualization output is generated further based on parameter input and the data includes vector chart data.

Abstract: Techniques related to training and implementing a bidirectional pairing architecture for object detection are discussed. Such techniques include generating a first enhanced feature map for each frame of a video sequence by processing the frames in a first direction, generating a second enhanced feature map for frame by processing the frames in a second direction opposite the first, and determining object detection information for each frame using the first and second enhanced feature map for the frame.