Patents by Inventor Maksim Kuzmenka
Maksim Kuzmenka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11949419Abstract: Methods, systems, and devices for delay adjustment circuits are described. Amplifiers (e.g., differential amplifiers) may act like variable capacitors (e.g., due to the Miller-effect) to control delays of signals between buffer (e.g., re-driver) stages. The gains of the amplifiers may be adjusted by adjusting the currents through the amplifiers, which may change the apparent capacitances seen by the signal line (due to the Miller-effect). The capacitance of each amplifier may be the intrinsic capacitance of input transistors that make up the amplifier, or may be a discrete capacitor. In some examples, two differential stages may be inserted on a four-phase clocking system (e.g., one on 0 and 180 phases, the other on 90 and 270 phases), and may be controlled differentially to control phase-to-phase delay.Type: GrantFiled: December 19, 2022Date of Patent: April 2, 2024Assignee: Micron Technology, Inc.Inventors: Maksim Kuzmenka, Elena Cabrera Bernal
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Publication number: 20240030902Abstract: Electronic devices for correcting a duty-cycle of a clock signal are disclosed. An electronic device may include circuitry configured to receive an input clock signal and generate, based on the input clock signal, a number of corrected clock signals. The circuitry may further be configured to generate, via an amplifier of the circuitry, a number of error signals based on the number of corrected clock signals and adjust a duty cycle of the number of corrected clock signals based on the number of error signals. Further, the circuitry may be configured to disable the amplifier in response to determining that the input clock signal is disabled. Associated apparatuses and methods are also disclosed.Type: ApplicationFiled: September 29, 2023Publication date: January 25, 2024Inventors: Maksim Kuzmenka, Elena Cabrera Bernal
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Publication number: 20240029779Abstract: A memory device may include memory cell array a clock circuit configured to generate a plurality of clock signals for access operations associated with the memory cell array. The clock circuit may include a ring oscillator circuit that is configured to equalize phase distortions of the plurality of clock signals.Type: ApplicationFiled: July 19, 2022Publication date: January 25, 2024Inventors: Maksim KUZMENKA, Fabien FUNFROCK
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Patent number: 11791805Abstract: Apparatuses and methods for correcting a duty-cycle of a clock signal are disclosed. An apparatus includes a duty-cycle adjuster, a circuit, and a clock detector. The duty-cycle adjuster is configured to receive an input clock signal and correct a duty-cycle of a corrected clock signal relative to an input duty-cycle of the input clock signal. The circuit is configured to control corrections made to the duty-cycle of the corrected clock signal by the duty-cycle adjuster. The clock detector is configured to disable the corrections made to the duty-cycle of the corrected clock signal responsive to a detection that the input clock signal is disabled.Type: GrantFiled: June 16, 2022Date of Patent: October 17, 2023Inventors: Maksim Kuzmenka, Elena Cabrera Bernal
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Publication number: 20230187302Abstract: Systems for cooling semiconductor devices that can comprise a heatsink and a cleaning element for the heatsink. The heatsink can have fins spaced apart from each other by channels. The cleaning element can have a base and one or more arms extending from the base. The cleaning element can be positioned with respect to the heatsink such that each arm is aligned with a corresponding channel between the fins, and the arms are moveable between a flow configuration in which the arms are in the channels and a cleaning configuration in which the arms are outside of the channels.Type: ApplicationFiled: February 9, 2023Publication date: June 15, 2023Inventor: Maksim Kuzmenka
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Publication number: 20230119349Abstract: Methods, systems, and devices for delay adjustment circuits are described. Amplifiers (e.g., differential amplifiers) may act like variable capacitors (e.g., due to the Miller-effect) to control delays of signals between buffer (e.g., re-driver) stages. The gains of the amplifiers may be adjusted by adjusting the currents through the amplifiers, which may change the apparent capacitances seen by the signal line (due to the Miller-effect). The capacitance of each amplifier may be the intrinsic capacitance of input transistors that make up the amplifier, or may be a discrete capacitor. In some examples, two differential stages may be inserted on a four-phase clocking system (e.g., one on 0 and 180 phases, the other on 90 and 270 phases), and may be controlled differentially to control phase-to-phase delay.Type: ApplicationFiled: December 19, 2022Publication date: April 20, 2023Inventors: Maksim Kuzmenka, Elena Cabrera Bernal
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Patent number: 11581236Abstract: Systems for cooling semiconductor devices that can comprise a heatsink and a cleaning element for the heatsink. The heatsink can have fins spaced apart from each other by channels. The cleaning element can have a base and one or more arms extending from the base. The cleaning element can be positioned with respect to the heatsink such that each arm is aligned with a corresponding channel between the fins, and the arms are moveable between a flow configuration in which the arms are in the channels and a cleaning configuration in which the arms are outside of the channels.Type: GrantFiled: February 14, 2020Date of Patent: February 14, 2023Assignee: Micron Technology, Inc.Inventor: Maksim Kuzmenka
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Patent number: 11563427Abstract: Methods, systems, and devices for delay adjustment circuits are described. Amplifiers (e.g., differential amplifiers) may act like variable capacitors (e.g., due to the Miller-effect) to control delays of signals between buffer (e.g., re-driver) stages. The gains of the amplifiers may be adjusted by adjusting the currents through the amplifiers, which may change the apparent capacitances seen by the signal line (due to the Miller-effect). The capacitance of each amplifier may be the intrinsic capacitance of input transistors that make up the amplifier, or may be a discrete capacitor. In some examples, two differential stages may be inserted on a four-phase clocking system (e.g., one on 0 and 180 phases, the other on 90 and 270 phases), and may be controlled differentially to control phase-to-phase delay.Type: GrantFiled: June 18, 2021Date of Patent: January 24, 2023Assignee: Micron Technology, Inc.Inventors: Maksim Kuzmenka, Elena Cabrera Bernal
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Publication number: 20230006659Abstract: Apparatuses and methods for correcting a duty-cycle of a clock signal are disclosed. An apparatus includes a duty-cycle adjuster, a circuit, and a clock detector. The duty-cycle adjuster is configured to receive an input clock signal and correct a duty-cycle of a corrected clock signal relative to an input duty-cycle of the input clock signal. The circuit is configured to control corrections made to the duty-cycle of the corrected clock signal by the duty-cycle adjuster. The clock detector is configured to disable the corrections made to the duty-cycle of the corrected clock signal responsive to a detection that the input clock signal is disabled.Type: ApplicationFiled: June 16, 2022Publication date: January 5, 2023Inventors: Maksim Kuzmenka, Elena Cabrera Bernal
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Publication number: 20220407505Abstract: Methods, systems, and devices for delay adjustment circuits are described. Amplifiers (e.g., differential amplifiers) may act like variable capacitors (e.g., due to the Miller-effect) to control delays of signals between buffer (e.g., re-driver) stages. The gains of the amplifiers may be adjusted by adjusting the currents through the amplifiers, which may change the apparent capacitances seen by the signal line (due to the Miller-effect). The capacitance of each amplifier may be the intrinsic capacitance of input transistors that make up the amplifier, or may be a discrete capacitor. In some examples, two differential stages may be inserted on a four-phase clocking system (e.g., one on 0 and 180 phases, the other on 90 and 270 phases), and may be controlled differentially to control phase-to-phase delay.Type: ApplicationFiled: June 18, 2021Publication date: December 22, 2022Inventors: Maksim Kuzmenka, Elena Cabrera Bernal
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Patent number: 11437086Abstract: Methods, systems, and devices for phase clock correction are described. The clock correction may, in some examples, include two stages of duty cycle adjustment. In a first stage, the duty cycles of multiple clock signals may be adjusted. These clock signals may be based on an input clock signal and its complement. The duty cycle adjustment provided to a clock signal during this stage may be based on a difference between the duty cycle of the clock signal before adjustment and the duty cycle of another clock signal. In the second stage, the duty cycle of the input clock signal and its complement may be adjusted. The duty cycle adjustment provided to the input clock signal and/or its complement may be based on clock signals generated from the multiple clock signals after their duty cycles have been adjusted.Type: GrantFiled: July 13, 2021Date of Patent: September 6, 2022Assignee: Micron Technology, Inc.Inventors: Martin Brox, Maksim Kuzmenka
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Patent number: 11368142Abstract: Apparatuses and methods for correcting a duty-cycle of a clock signal are disclosed. An apparatus includes an integrator circuit, an amplifier circuit, and an electrically controllable switch. The integrator circuit is configured to provide an integrator signal indicating substantially an integral of a corrected clock signal. The amplifier circuit is configured to be disabled responsive to a detection that an input clock signal is disabled. The amplifier circuit includes a first amplifier input terminal and a second amplifier input terminal. The electrically controllable switch is configured to selectively electrically connect the first amplifier input terminal to the second amplifier input terminal responsive to the detection that the input clock signal is disabled. A method of correcting a duty-cycle of an input clock signal includes adjusting a corrected duty-cycle of the corrected clock signal responsive to a first error signal and a second error signal from the amplifier circuit.Type: GrantFiled: July 2, 2021Date of Patent: June 21, 2022Assignee: Micron Technology, Inc.Inventors: Maksim Kuzmenka, Elena Cabrera Bernal
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Patent number: 11251796Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.Type: GrantFiled: November 16, 2020Date of Patent: February 15, 2022Assignee: Micron Technology, Inc.Inventors: Yasuhiro Takai, Maksim Kuzmenka, Mani Balakrishnan, Martin Brox
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Publication number: 20210407575Abstract: Methods, systems, and devices for phase clock correction are described. The clock correction may, in some examples, include two stages of duty cycle adjustment. In a first stage, the duty cycles of multiple clock signals may be adjusted. These clock signals may be based on an input clock signal and its complement. The duty cycle adjustment provided to a clock signal during this stage may be based on a difference between the duty cycle of the clock signal before adjustment and the duty cycle of another clock signal. In the second stage, the duty cycle of the input clock signal and its complement may be adjusted. The duty cycle adjustment provided to the input clock signal and/or its complement may be based on clock signals generated from the multiple clock signals after their duty cycles have been adjusted.Type: ApplicationFiled: July 13, 2021Publication date: December 30, 2021Inventors: Martin Brox, Maksim Kuzmenka
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Publication number: 20210257271Abstract: Systems for cooling semiconductor devices that can comprise a heatsink and a cleaning element for the heatsink. The heatsink can have fins spaced apart from each other by channels. The cleaning element can have a base and one or more arms extending from the base. The cleaning element can be positioned with respect to the heatsink such that each arm is aligned with a corresponding channel between the fins, and the arms are moveable between a flow configuration in which the arms are in the channels and a cleaning configuration in which the arms are outside of the channels.Type: ApplicationFiled: February 14, 2020Publication date: August 19, 2021Inventor: Maksim Kuzmenka
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Patent number: 11069397Abstract: Methods, systems, and devices for phase clock correction are described. The clock correction may, in some examples, include two stages of duty cycle adjustment. In a first stage, the duty cycles of multiple clock signals may be adjusted. These clock signals may be based on an input clock signal and its complement. The duty cycle adjustment provided to a clock signal during this stage may be based on a difference between the duty cycle of the clock signal before adjustment and the duty cycle of another clock signal. In the second stage, the duty cycle of the input clock signal and its complement may be adjusted. The duty cycle adjustment provided to the input clock signal and/or its complement may be based on clock signals generated from the multiple clock signals after their duty cycles have been adjusted.Type: GrantFiled: April 1, 2019Date of Patent: July 20, 2021Assignee: Micron Technology, Inc.Inventors: Martin Brox, Maksim Kuzmenka
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Publication number: 20210075428Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal, To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.Type: ApplicationFiled: November 16, 2020Publication date: March 11, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Yasuhiro Takai, Maksim Kuzmenka, Mani Balakrishnan, Martin Brox
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Publication number: 20210058090Abstract: Disclosed herein is an apparatus that includes a phase frequency detector configured to compare a phase difference between first and second clock signals to generate a phase detection signal, and a slew rate controller configured to lower a slew rate of the first clock signal when a selection signal is in a first state.Type: ApplicationFiled: August 22, 2019Publication date: February 25, 2021Applicant: Micron Technology, Inc.Inventors: Yasuhiro Takai, Martin Brox, Mani Balakrishnan, Maksim Kuzmenka
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Patent number: 10931287Abstract: Disclosed herein is an apparatus that includes a phase frequency detector configured to compare a phase difference between first and second clock signals to generate a phase detection signal, and a slew rate controller configured to lower a slew rate of the first clock signal when a selection signal is in a first state.Type: GrantFiled: August 22, 2019Date of Patent: February 23, 2021Assignee: Micron Technology, Inc.Inventors: Yasuhiro Takai, Martin Brox, Mani Balakrishnan, Maksim Kuzmenka
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Patent number: 10840918Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.Type: GrantFiled: March 28, 2019Date of Patent: November 17, 2020Assignee: Micron Technology, Inc.Inventors: Yasuhiro Takai, Maksim Kuzmenka, Mani Balakrishnan, Martin Brox