Abstract: An integrated circuit includes a circuit for adjusting a voltage drop. The circuit includes a reference voltage node, an output node and a driver circuit coupled between the reference voltage node and the output node. The driver circuit includes an impedance causing a current flow through the driver circuit when a reference voltage is applied to the reference voltage node. A current source is coupled to the driver circuit to impress an adjustment current based on a control current such that the current flow through the driver circuit is adjusted to yield a desired voltage drop across the driver circuit.

Abstract: The invention relates to a semiconductor memory module having a plurality of memory chips arranged in at least one row and at least one buffer chip which drives and receives clock signals and command and address signals to the memory chips and data signals to and from the memory chips via a clock, address, command and data bus inside the module and which forms an interface to an external primary memory bus. The semiconductor memory module has an even number of buffer chips arranged on it and all of the memory chips are connected to two respective buffer chips at least by one signal line type from a signal group and just to one of the two buffer chips by the remaining signal lines from the group.

Abstract: The present invention relates to a memory arrangement having a controller and having at least one memory device. Data signals, control signals and address signals can be transferred between the controller and the memory device. The memory arrangement is designed in such a way that the data signals can be transferred via data signal lines between the controller and the memory device. The memory arrangement is furthermore designed in such a way that the control signals and the address signals can likewise be transferred via the data signal lines between the controller and the memory device.

Abstract: Embodiments of the invention provide a memory arrangement having an even number k=4 of physically spaced RAM chips, on each of which it is possible for m data items to be simultaneously written or read via an m-bit data bus, also having a register for buffer-storing and transmitting n respective parallel data bits as a packet between an n-bit parallel port and the data buses, and having a selection device which responds to selection bits in order to select a respective separate cell group within the plurality of the chips for each of the disjoint m-bit groups (d) of the n-bit packet. The k chips are classified into q=2 disjoint chip groups, each of which comprises k/q chips which differ as little as possible from one another in terms of their distance from the register. The number m is chosen to be equal to q*n/k, and the selection device is designed to select a respective separate chip from the same chip group and a cell group in this chip for each m-bit group of the same n-bit packet.

Abstract: A circuit exhibits a signal input, means for determining a reference level on the basis of properties of a signal received at the signal input. In addition, the circuit further exhibits means for evaluating the signal on the basis of the reference level.

Abstract: In an output driver circuit, the signal propagation time of an electrical signal which is to be transmitted between two selected driver stages is ascertained. If the ascertained signal propagation time is at least equal to half the period duration of the signal which is to be transmitted, the signal to be transmitted is delayed between the two selected driver stages such that a given signal edge change appears at the output of the other of the selected driver stages at a different time from other signal edge which follow the one given signal edge change in time, at driver stages which are situated upstream of the other of the selected driver stages. The inventive output driver circuit accordingly has a delay element which can be used to influence the signal propagation time between the selected driver stages.

Abstract: A circuit arrangement for converting logic signal levels has a level converter and a mixing arrangement for influencing a pulse width. The level converter includes a first signal path and a second signal path each having a series circuit comprising two transistors of different conductivity types and two outputs which are each connected to a tap between the transistors which are coupled in series. In this case, the transistors of one conductivity type can be controlled by means of a push-pull signal and the transistors of the other conductivity type in a respective one of the two signal paths can be controlled by means of a signal at the output of the respective other signal path. The mixing arrangement includes two inputs and two outputs, the first input being coupled to the first output and the second input being coupled to the second output.

Abstract: A circuit board comprises a dielectric layer, a net of first power supply lines for providing a first reference voltage plane and a net of second power supply lines for providing a second reference voltage plane. The nets of first and second power supply lines are arranged such that first power supply lines and second power supply lines are alternately arranged in the direction of a first surface of the dielectric layer.

Abstract: A device for distributing a signal, in particular a clock signal or a command/address signal from a signal source to a plurality of circuit units, includes a transformer. The transformer has a primary winding receiving the signal from the signal source. Further, the transformer includes a plurality of secondary windings, which are arranged to interact with the primary winding to transfer the signal to the circuit units.

Abstract: The invention relates to a semiconductor memory module having a plurality of memory chips arranged next to one another in a row. The memory module has a module-internal clock, command/address and data bus which transfers clock signal, command and address signals and also data signals from a memory controller device to the memory chips and data signals from the memory chips to the memory controller device. The memory module has respective clock, command/address and data signal lines. The clock signal lines comprise two differential clock signal lines which, at their end opposite to the memory controller device are either open or connected to one another by a short-circuiting bridge. The memory chips, during a write operation, synchronize the write data with the clock signal running from the memory controller device to the end of the clock signal line and, during a read operation, output the read data synchronously with the clock signal reflected from the open or short-circuited end of the clock signal lines.

Abstract: A circuit module has a module board and a plurality of circuit chips that are arranged on the module board. A module main bus having a plurality of lines of the circuit module branches into a plurality of sub-buses having a plurality of lines. Each of the sub-buses is connected to one of the circuit chips. Each circuit chip has an indication signal generating unit for providing an indication signal based on a combination of the signals received on the plurality of lines of the sub-bus connected to the respective circuit chip, and an indication signal output for outputting the indication signal.

Abstract: A circuit system has a main bus, a circuit module connected to a sub-bus, a saturable magnetic switch connected between the sub-bus and the main bus, wherein the saturable magnetic switch has a first inductance in a first saturation state and a second inductance in a second saturation state, the first inductance being lower than the second inductance, a unit for placing the magnetic switch in the first saturation state for coupling the sub-bus to the main bus, or for placing saturable magnetic switch in the second saturation state for decoupling the sub-bus from the main bus.

Abstract: An ESD protection apparatus for an electrical device with a circuit structure having an internal terminal, which is connected to an external terminal of the electrical device via a conductive connection, has a gas-filled cavity, through which the conductive connection extends at least partly, and a reference electrode in the cavity, wherein the conductive connection is disposed such in the cavity, that when applying a potential exceeding a predetermined threshold to the external terminal, a gas discharge occurs from the conductive connection to the reference electrode.

Abstract: A branched command/address bus architecture between a memory register and a plurality of memory units includes a main bus connected to the memory register. A first sub-bus is connected to the main bus and branches into a first number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same. A second sub-bus is also connected to the main bus and branches into a second number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same, wherein the second number is smaller than the first number. Further, the second sub-bus branches into a number of auxiliary buses, wherein the number of auxiliary buses corresponds to the difference between the first number and the second number, wherein each auxiliary bus is capacitively loaded corresponding to the memory unit buses and does not serve for driving a memory unit.

Abstract: To provide a circuit board with improved electrical features with respect to a synchronization of signals, a circuit board comprises a dielectric substrate and a trace extending along a surface of the dielectric substrate, the trace having a first and second portion, the trace being covered by a first medium at the first portion, wherein the first medium is formed by an encapsulation element of a dielectric material so that the effective dielectric constant of the first medium is different from the effective dielectric constant of a medium extending over the trace at the second portion. Thus, a propagation speed difference can be created, when a signal travels along the first portion of the trace with respect to a signal propagation speed of a signal traveling along the second portion of the trace.

Abstract: A device for converting an input signal having a bipolar pulse with a positive part and a negative part of same duration, into a difference signal includes a delay member with an input for receiving the input signal and an output. The delay member delays the input signal in order to obtain a delayed signal and outputs the delayed signal to the output. The device further includes a differential amplifier with a first input for receiving the input signal, a second input for receiving the delayed signal, and an output for outputting the difference signal formed from the input signal and the delayed signal.

Abstract: Embodiments of the invention provide a memory arrangement having an even number k=4 of physically spaced RAM chips, on each of which it is possible for m data items to be simultaneously written or read via an m-bit data bus, also having a register for buffer-storing and transmitting n respective parallel data bits as a packet between an n-bit parallel port and the data buses, and having a selection device which responds to selection bits in order to select a respective separate cell group within the plurality of the chips for each of the disjoint m-bit groups (d) of the n-bit packet. The k chips are classified into q=2 disjoint chip groups, each of which comprises k/q chips which differ as little as possible from one another in terms of their distance from the register. The number m is chosen to be equal to q*n/k, and the selection device is designed to select a respective separate chip from the same chip group and a cell group in this chip for each m-bit group of the same n-bit packet.

Abstract: A circuit system includes a means for controlling a first and a second memory unit by means of a differential control signal. The differential control signal includes a first control signal and a second control signal, which is inverted to the first control signal. Further, the circuit system comprises a differential control signal line, which includes a first signal line for routing the first control signal and a second signal line for routing the second control signal. The first switching unit is connected via the first signal line and the second circuit unit is connected via the second signal line to the means for controlling.

Abstract: In a memory module for a memory configuration having a bus system made up of a plurality of signal lines, each signal line has respectively been produced essentially without any stub continuously from a supplying contact device to a discharging contact device, disposed close to the supplying contact device, in order to increase a maximum data transmission rate within the memory configuration. Between the supplying contact device and the discharging contact device, each of the signal lines is routed in succession at minimum distances via connection elements associated with the signal line on memory chips associated with the signal line.

Abstract: A circuit module comprises a first circuit chip (102a) and a second circuit chip (102b). Each circuit chip comprises a signal input (104a, 104b) and a reference input (106a, 106b). A first termination resistance (112) connects the signal inputs (104a, 104b) and a second resistance (114) connects the reference inputs (106a, 106b). A first termination resistance (116) connects the second signal input (104b) to the termination voltage (120) and a second termination resistance (118) connects the second reference input (106b) to the termination voltage (120). A first ratio between the first resistance (112) and the first termination resistance (116) corresponds to a second ratio between the second resistance (114) and the second termination resistance (118).