Abstract: In an output driver circuit, the signal propagation time of an electrical signal which is to be transmitted between two selected driver stages is ascertained. If the ascertained signal propagation time is at least equal to half the period duration of the signal which is to be transmitted, the signal to be transmitted is delayed between the two selected driver stages such that a given signal edge change appears at the output of the other of the selected driver stages at a different time from other signal edge which follow the one given signal edge change in time, at driver stages which are situated upstream of the other of the selected driver stages. The inventive output driver circuit accordingly has a delay element which can be used to influence the signal propagation time between the selected driver stages.

Abstract: A memory module has a module board having a main surface. A plurality of memory chips is arranged on the main surface of the module board. Each memory chip has two main surfaces extending between a first end face and a second end face of the memory chip, first mounting sites mounted to the main surface of the module board, and second mounting sites spaced apart from the first mounting sites and mounted to support sites spaced apart from the module board, so that a distance between the first end face and the module board is greater than a distance between the second end face and the module board. A circuit chip suited for such a memory module has terminals for connecting a circuitry of the circuit chip to terminals on the motherboard. Moreover, conductive structures are provided on a surface of the circuit chip for connecting terminals of another circuit chip to terminals on the motherboard.

Abstract: The invention relates to a semiconductor memory module having at least one memory chip and a buffer chip, which drives clock, address and command signals to the memory chip and drives data signals to, and receives them from, the memory chip via a module-internal clock, address, command and data bus. The buffer chip forms an interface to an external memory main bus. The data bus lines and/or the clock, command and address bus lines are respectively connected to the buffer chip at their two ends and are capable of being driven by the buffer chip from these two ends. Control means are being provided and set up in such a manner that they respectively match the directions of propagation of the data signals and of the clock, command and address signals on the corresponding bus lines during writing and reading.

Abstract: A circuit for transmitting a signal has a first signal line and a second signal line, wherein the second signal line is arranged adjacent to the first signal line, such that an interaction between signals being transmitted on the signal lines takes place. The circuit further comprises a first driver for driving a first signal on the first signal line, wherein the first signal comprises a delay. A second driver is configured for driving a second signal on the second signal line depending on the delay of the first signal, such that the delay of the first signal is adjusted due to the interaction of the second signal on the first signal. A method and computer program are also disclosed.

Abstract: A clock generator includes an interface for receiving a plurality of n periodical signals of the same frequency which are phase-shifted with respect to each other, wherein n/3. Further, a clock signal generator is provided for generating respective clock edges of a clock signal if at least two of the phase-shifted signals fulfill a predetermined relationship with respect to each other, wherein the clock signal has a frequency which is n or 2n times the frequency of the phase-shifted signals.

Abstract: An ESD protection apparatus for an electrical device with a circuit structure having an internal terminal, which is connected to an external terminal of the electrical device via a conductive connection, has a gas-filled cavity, through which the conductive connection extends at least partly, and a reference electrode in the cavity, wherein the conductive connection is disposed such in the cavity, that when applying a potential exceeding a predetermined threshold to the external terminal, a gas discharge occurs from the conductive connection to the reference electrode.

Abstract: A circuit for coupling a logic signal from a circuit input to a circuit output includes a parallel connection of a first circuit branch and a second circuit branch, wherein an inverter in the first branch powered as last inverter in this branch via first supply terminals, via which a first supply potential and a second supply potential are supplied, and an inverter in the second branch powered as first inverter in this branch via second supply voltage terminals, via which a second supply potential and a second reference potential are supplied, are adapted to receive the same logic value of the logic signal, wherein outputs of the two circuit branches are connected to each other and coupled to the circuit output. In such a circuit, propagation time differences of rising and falling edges, which may develop by fluctuation of various supply potentials, may be minimized.

Abstract: A device for supplying control signals to memory units of a memory module comprises a first bus section for supplying a first part of the control signals to a first memory unit. In addition, a second bus section is provided for supplying a second part of the control signals to a second memory unit. Finally, the device comprises redrive means for redriving the first part of the control signals from the first memory unit to the second memory unit and for redriving the second part of the control signals from the second memory unit to the first memory unit. A memory unit for such a device for supplying control signals comprises first inputs for receiving a first part of the control signals from a memory control, second inputs for receiving a second part of the control signals from at least one other memory unit, and outputs for redriving said first part of the control signals to said at least one other memory unit.

Abstract: A circuit exhibits a signal input, means for determining a reference level on the basis of properties of a signal received at the signal input. In addition, the circuit further exhibits means for evaluating the signal on the basis of the reference level.

Abstract: A circuit comprises a first supply line and a second supply line. A capacitor is arranged between the first supply line and the second supply line. The first supply line and the second supply line are inductively coupled, such that a switching current on the second supply line induces a compensating current into the first supply line. The compensating current compensates the switching current by flowing from the second supply line over the capacitor into the first supply line.

Abstract: A memory system has a circuit board provided with a first slot connector into which a first memory module is inserted. A second slot connector is provided into which a second memory module is inserted. The first and the second memory modules are connected via a flexible bridge. The flexible bridge extends from respective ends of the memory modules opposite to that ends thereof which are inserted into the connector slots. The flexible bridge provides a signal bus between the memory modules.

Abstract: The invention relates to an FBGA arrangement, comprising a substrate on which at least one chip is chip-bonded face-down, which has a central row of bonding pads connected to contact islands (landing pads) on the substrate by a bonding channel in the substrate via wire bridges, which substrate, for its part, is provided with soldering balls—arranged in an array—for contact connection to a printed circuit board, and the contact islands and the soldering balls being connected to one another via a rewiring of the substrate. The preferred embodiment of the invention is intended to provide an FBGA arrangement which supports the center pad row technology and at the same time has low electrical parasitics.

Abstract: Memory modules without signal-conditioning devices (unbuffered, unregistered) are provided in a system by using adapter cards that have signal-conditioning devices and are then operated in the manner of memory modules with signal-conditioning devices (buffered, registered). Systems can thereby be expanded in a very simple manner and can be flexibly adapted according to requirements, and for this purpose only one type (unbuffered, unregistered) of memory module is required.

Abstract: A circuit board comprises a dielectric layer, a net of first power supply lines for providing a first reference voltage plane and a net of second power supply lines for providing a second reference voltage plane. The nets of first and second power supply lines are arranged such that first power supply lines and second power supply lines are alternately arranged in the direction of a first surface of the dielectric layer.

Abstract: A circuit board comprises a dielectric layer with a through-hole between a first and a second surface of the dielectric layer. An electrically conductive coating is arranged on a wall of the through-hole between the first and the second surface and a first signal trace is arranged on the first surface and a second signal trace is arranged on the second surface of the dielectric layer. The wire passing through the through-hole connects the first signal trace to the second signal trace.

Abstract: A device is provided for accessing circuit units via access registers. The circuit units have a plurality of inputs for access to said circuit units. A first access register having register outputs which are connected to a first part of the inputs of at least one first circuit unit, and having register outputs which are connected to inputs of at least one second circuit unit is provided. In addition, a second access register having register outputs which are connected to a second part of the inputs of said at least one first circuit unit, and having register outputs connected to inputs of at least one third circuit unit is provided.

Abstract: A connector has a connector body, at least one contact and at least one bimetal stripe. One end of the contact is fixed to the connector body and another end of each contact extends from a surface of the connector body forming a springy contact. One end of the bimetal stripe is fixed in the connector body and another end of the bimetal stripe extends from the surface of the connector body. The bimetal stripe is arranged for moving the contact in a first or second position depending on the temperature of the bimetal stripe.

Abstract: The invention relates to a semiconductor memory module having a plurality of memory chips and at least one buffer chip, which drives clock signals and command and address signals to the memory chips and also drives data signals to, and receives them from, the memory chips via a module-internal clock, address, command and data signal bus. The buffer chip forms an interface to an external memory main bus and the memory chips are arranged in at least one row.

Abstract: An apparatus for transmitting a first signal (102) and a second signal (104) on a first transmission path (122) and a second transmission path (124), wherein the first and the second transmission path (122, 124) are arranged such that a cross-talk between the transmission paths (122, 124) takes place when the first and the second signals (102, 104) are transmitted on the first and the second transmission path (122, 124). The apparatus comprises a first means (112) for driving the first signal (102) on the first transmission path (122) and a means (108) for delaying the second signal (104) by a delay time period and for providing a delayed signal (104?) and a second means (114) for driving the delayed signal on the second transmission path (124). The delay time period is such that rising and falling edges of the first signal (102) and the delayed signal (104?) do not coincide.

Abstract: To provide a circuit board with improved electrical features with respect to a synchronization of signals, a circuit board comprises a dielectric substrate and a trace extending along a surface of the dielectric substrate, the trace having a first and second portion, the trace being covered by a first medium at the first portion, wherein the first medium is formed by an encapsulation element of a dielectric material so that the effective dielectric constant of the first medium is different from the effective dielectric constant of a medium extending over the trace at the second portion. Thus, a propagation speed difference can be created, when a signal travels along the first portion of the trace with respect to a signal propagation speed of a signal traveling along the second portion of the trace.